Encountering Gate Oxide Breakdown Encountering Gate Oxide Breakdown - PowerPoint PPT Presentation

Encountering Gate Oxide Breakdown Encountering Gate Oxide Breakdown with with Shadow Transistors Shadow Transistors Shadow Transistors to Shadow Transistors to to Increase Reliability to Increase Reliability Increase Reliability Increase Reliability Claas Cornelius 1 , Frank Sill 2 , Hagen Sämrow 1 , Jakob Salzmann 1 , Dirk Timmermann 1 , Diógenes Cecílio da Silva Jr. 2 , g 1 University of Rostock, Germany 2 Federal University of Minas Gerais (UFMG), Brazil Gramado, 3 rd September 2008 1

Focus / Main ideas Focus / Main ideas 1 1. Reliability regarding oxide breakdown Reliability regarding oxide breakdown 2 2. Transistor / Gate level approach Transistor / Gate level approach 3. Selective insertion / thick oxide devices Cornelius et. al: Shadow Transistors 2

Outline Outline � Motivation – Technology development T h l d l t – Error classification – Time-Dependent Dielectric Breakdown (TDDB) Ti D d t Di l t i B kd (TDDB) � Shadow Transistors – Used model U d d l – Main Ideas – Algorithm Al ith � Results � Conclusion Cornelius et. al: Shadow Transistors 3

Motivation Motivation Technology development Wolfdale 500 150 nm 410 Mill. 130 nm 130 nm s [Mill.] 400 ology 90 nm 100 nm 300 300 ansistors Techno 65 nm 200 Prescott 45 nm 50 nm 125 Mill. Northwood Northwood Tra 100 55 Mill. Yonah, 151 Mill. 0 0 nm 2002 2004 2006 2008 Year Probability for failures increases due to: Probability for failures increases due to: � Increasing transistor count � Shrinking technology Cornelius et. al: Shadow Transistors 4

Motivation Motivation Error classification Error Temporary Permanent Soft errors, Voltage drop, Coupling, … Reduced Performance Malfunction Process variations, Electro- Electromigration, migration, Oxide wearout ... Oxide breakdown ... Oxide wearout Oxide breakdown Cornelius et. al: Shadow Transistors 5

Motivation Motivation Time-Dependent Dielectric Breakdown (TDDB) � Tunneling currents g Wear out of gate oxide � Creation of conducting path g p between Gate and Substrate, Drain, Source � Depending on electrical field over gate oxide, temperature (exp.) , Source: Pey&Tung and gate oxide thickness (exp.) ( ) Also: abrupt damage due to � extreme overvoltage (e.g. Electro- t lt ( El t Static Discharge) Source: Pey&Tung Cornelius et. al: Shadow Transistors 6

Motivation Motivation TDDB ─ Trends Increasing probability for Gate-Oxide-Breakdown 16 10000 pe β ) ox Weibull slop t Density Jo 12 1000 8 100 high-k? eliability (W Current 4 10 0 0 1 1 Re 0 2 4 6 8 10 12 180 nm 90 nm 45 nm 22 nm Gate Oxide Thickness [nm] Technology Source: Borkar, Intel Source: Kauerauf, EDL, 2002 Cornelius et. al: Shadow Transistors 7

Shadow Transistors Shadow Transistors Applied model TDDB between gate and channel TDDB between gate and channel Gate For an Inverter, 65nm-BPTM: , Gate Oxide 100% 20 Source Drain 75% 75% 15 15 V out /V DD 50% 10 rel. delay Model: Model: 25% 5 R GC 0% 0 ‐ R GC [k Ω ] → W 2 W 1 W= W 1 +W 2 Based on: Segura et. al., “A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level” 1995. i MOS T i t T ti I li ti t Ci it L l” 1995 Cornelius et. al: Shadow Transistors 8

Shadow Transistors Shadow Transistors Applied model TDDB between gate and source/drain TDDB between gate and source/drain Gate For an Inverter, 65nm-BPTM: , Gate Oxide Source Drain 100% V out /V DD V /V 75% 50% Model: Model: 25% 0% 0% ‐ R GC [k Ω ] → Based on: Segura et. al., “A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level” 1995. i MOS T i t T ti I li ti t Ci it L l” 1995 Cornelius et. al: Shadow Transistors 9

Shadow Transistors Shadow Transistors Main idea (1) ─ Parallel transistors 1 1. Insertion of additional transistors in Insertion of additional transistors in parallel to vulnerable transistors Shadow transistors (ST) Shadow transistors (ST) V DD /V out Relative Delay 10 100% wo/ ST 8 8 75% w/ ST 6 50% w/ ST 4 wo/ ST 25% 25% 2 2 0 0% R GC [k Ω ] → ‐ ‐ R GC [k Ω ] → For an Inverter 65nm BPTM For an Inverter, 65nm-BPTM Cornelius et. al: Shadow Transistors 10

Shadow Transistors Shadow Transistors Main idea (2) ─ Thick gate oxides 2 2. Application of H-Vt/To transistors with: Application of H Vt/To transistors with: – Higher threshold voltage – Thicker gate oxide Thicker gate oxide Less vulnerable to TDDB Δ Δ 0.15 t t MTTF MTTF ox ox = = − H Vt To / 0.22 10 4.81 10 0.22 MTTF − / L Vt To MTTF – Mean Time To Failure Source: Srinivasan, “RAMP: A Model for Reliability Aware Microprocessor Design” Stathis, J., “Reliability Limits for the Gate Insulator in CMOS Technology” St thi J “R li bilit Li it f th G t I l t i CMOS T h l ” Cornelius et. al: Shadow Transistors 11

Shadow Transistors Shadow Transistors Main idea (3) ─ Selective insertion 3 3. Selective insertion of shadow transistors in parallel to vulnerable Selective insertion of shadow transistors in parallel to vulnerable transistors: – Component reliability depends on p y p Activity, state, temperature, size, fabrication … Most vulnerable can be identified Shadow transistors N tli t Netlist only added in parallel modification to most vulnerable devices. Cornelius et. al: Shadow Transistors 12

Shadow Transistors Shadow Transistors Main idea (3) ─ Selective insertion 3 3. Selective insertion of shadow transistors in parallel to vulnerable Selective insertion of shadow transistors in parallel to vulnerable transistors: – Component reliability depends on p y p O Our Approach A h Activity, state, temperature, size, fabrication … � Estimation of stress factors Most vulnerable can be identified � � Determination of components reliability Determination of components reliability � Adding redundancy only at most vulnerable components � Advantage: Lower area, power and delay penalty compared to complete redundancy or random insertion [Sri04] Shadow transistors Netlist N tli t Source: [Sri04] Sirisantana, D&T, 2004 Source: [Sri04] Sirisantana D&T 2004 only added in parallel modification to most vulnerable devices. Cornelius et. al: Shadow Transistors 13

Shadow Transistors Shadow Transistors Main ideas ─ Discussion Advantages g � Increased reliability in respect to TDDB � H-Vt/To: Reliability increases by ~5x (for ∆ t ox = 0.15 nm) � Remarkable increase of system life time Drawbacks Drawbacks � Higher input capacity → higher delay and dynamic power dissipation Area increase Area increase � Remarks � Only slight improvements for Gate-Drain/Source breakdown � H-Vt/To has to be supported by technology Cornelius et. al: Shadow Transistors 14

Shadow Transistors Shadow Transistors Algorithm Estimation of logical Signal Estimation of logical Signal Probabilities (SP) Insertion of Shadow transistors where SP is lower (PMOS) than ( ) threshold value SP th or higher (NMOS) than 1 - SP th Modification of SP th Modification of SP th depending on ∆ t d / MTTF Estimation of delay increase ∆ t d and new Mean Time To Failure (MTTF) Cornelius et. al: Shadow Transistors 15

Results Results Improvement MTTF (L-Vt/To) ≈ 23 % additional transistors 20% B gards TDDB 15% MTTF as reg 10% emnet of M 5% Improve 0% c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 our algorithm random insertion Insertion of L ‐ Vt/To Shadow Transistors Cornelius et. al: Shadow Transistors 16

Results Results Performance Reduction (L-Vt/To) ≈ 23 % additional transistors 20% delay 15% of circuit's 10% Increase o 5% 0% c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 our algorithm random insertion Insertion of L ‐ Vt/To Shadow Transistors Cornelius et. al: Shadow Transistors 17

Results Results Application of H-Vt/To-ST ≈ 23 % additional transistors 60% DB egards TDD 45% MTTF as re 30% vemnet of M 15% Improv 0% c432 432 c499 499 c880 880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 1355 1908 2670 3540 5315 6288 7552 H ‐ Vt/To ‐ ST L ‐ Vt ‐ To ‐ ST Cornelius et. al: Shadow Transistors 18

Results Results Modification of C crit 250% DDB regards TD 200% of MTTF as 150% 100% ovemnet o 50% Impro 0% c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 SPth = 30 SPth = 55 Insertion of H ‐ Vt/To Shadow Transistors Cornelius et. al: Shadow Transistors 19

Conclusion Conclusion � System reliability decreases with shrinking technologies and rising transistor count transistor count Increasing probability of Time-Dependent Dielectric Breakdown � (TDDB) (TDDB) � Insertion of Shadow Transistors (ST) increases system lifetime � R Remarkable improvements by application of transistors with thick k bl i t b li ti f t i t ith thi k gate-oxide � S l Selective insertion of ST improves trade-off between reliability and ti i ti f ST i t d ff b t li bilit d performance � I Impact and amount of redundant transistors can be adapted by the t d t f d d t t i t b d t d b th threshold value SP th Cornelius et. al: Shadow Transistors 20