Comparison of Strategies for Redundancy to improve Reliability - PowerPoint PPT Presentation

Comparison of Strategies for Redundancy to improve Reliability concerning Gate Oxide Breakdown Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann 17.02.2009, Bremen Institut für Angewandte Mikroelektronik Universität Rostock und Datentechnik

Outline Basics and Motivation Approaches for reliability enhancements Gate oxide breakdown Redundancy strategies Theoretical fundamentals Results Conclusion / Outlook 2

Motivation – Known approaches Reliability Transient failures Permanent failures Failures occuring Initial failures at runtime Little effort put into Soft error resilience Yield enhancements lifetime reliability - Hardening techniques - Layout modifications enhancements - Reusing debug resources - Redundancy for redundant flipflops [Mitra] 3

Motivation – Known approaches Lifetime reliability enhancements High level: Dynamic system management to adapt operation conditions in response to an observed hardware usage [Srinivasan et al.] Low level: Random insertion of redundant transistors to improve yield [Sirisantana et al.] Improvement of this approach by a controlled insertion at those instances which are most vulnerable to gate oxide breakdown [Sill et al.] 4

Basics – Gate oxide breakdown Gate oxide breakdown – GOB: Point of time a conducting path between gate and substrate is generated Mainly dependent on: Gate oxide thickness Electrical field at the gate Causes: Sudden extrinsic overvoltage: ESD – Electro-Static Discharge Slow intrinsic destruction over time: TDDB – Time-Dependent Dielectric Breakdown 5

Basics – TDDB Physical mechanism: trap creation 6

Basics – TDDB Initial traps ������������ ��� � ��������� 7

Basics – TDDB Initial traps During operation: generation of overlapping traps ������������ ������������ ��� � ��� � ��������� ��������� 8

Basics – TDDB Initial traps During operation: generation of overlapping traps ������������ ������������ ������������ ��� � ��� � ��� � ��������� ��������� ��������� Soft breakdown: Creation of a conducting patch 9

Basics – TDDB Initial traps During operation: generation of overlapping traps ������������ ������������ ������������ ������������ � ��� � ��� � ��� � ��� � ��������� ��������� ��������� ��������� Soft breakdown: Increasing current flow Creation of a � Heat dissipation conducting patch � Thermal damage 10

Basics – TDDB Initial traps During operation: generation of overlapping traps ������������ ������������ ������������ ������������ ������������ � ��� � ��� � ��� � ��� � ��� � ��������� ��������� ��������� ��������� ��������� Soft breakdown: Increasing current flow Creation of a � Heat dissipation conducting patch � Thermal damage 11

Basics – TDDB Initial traps Finally: Hard breakdown ������������ ������������ ������������ ������������ ������������ ������������ R � 0 � ��� � ��� � ��� � ��� � ��� � ��� � ��������� ��������� ��������� ��������� ��������� ��������� 12

Basics – TDDB Finally: Hard breakdown Model by Segura et al. 13

Basics – Scaling issues Scaling increases the gate oxide breakdown problems: Increasing number of transistors within a die 14

Basics – Scaling issues Scaling increases the gate oxide breakdown problems: Increasing number of transistors within a die Decreasing gate oxide thickness Increase of the electrical field due to non-ideal supply voltage scaling ������� � ��� � ��� � � � � ����� � � �������� ��� ��� 15

Theoretical fundamentals Failure rate λ SYS represents the rate at which an individual system suffers from individual faults Reliability R sys (t) is the probability of the system to perform as desired at time t ( ) e λ − = SYS t R t SYS Series system with n equal components (component failure rate λ ) fails if any component fails [ ] n n ( ) ( )   = =  e λ − t R t R t  S Parallel system works until all of its components fail [ ] n n ( ) 1 1 ( ) 1  1  e λ − = − − = − − t R t R t   P 16

Theoretical fundamentals Mean Time To Failure ( MTTF SYS ) of a system is the average time a system operates until it fails ∞ = ∫ ( ) MTTF R t dt SYS SYS 0 17

Redundancy strategies n = no. of transistors; g = no. of gates; m = Ø no. of transistors per gate Basic multiplier ( ) − λ = n t R t e BASIC Block duplication 2 ( ) 1  1  − λ = − − n t R t e   BD Gate duplication g ( )  2  ( ) 1 1 = − − − λ m t R t e     GD Transistor duplication n ( )  2  ( ) 1 1 e λ − = − − t R t     TD 18

Simulation setup Wallace multiplier Transistor level simulations with HSpice Industrial 65 nm gate library First order model of Segura et al. 19

Results – No defects Ratio to basic multiplier [%] 200 150 100 50 0 Area Delay Overall Static power power Design Parameters Block duplication Gate duplication Transistor duplication 20

Results – Reliability with defects MTTF GOB + / - Dupl. No duplication 100.00 80.00 No 60.00 40.00 20.00 0.00 0.537 100 100 100 100 100 0 20 40 60 Block duplication Block 0.446 -17 % Gate duplication Gate 80 80 80 80 80 4.237 + 789 % Transistor duplication Trans. 13.552 + 2524 % 60 60 60 60 60 R(t) [%] R(t) [%] R(t) [%] R(t) [%] R(t) [%] 100 80 40 40 40 40 40 60 R(t) [%] 40 20 20 20 20 20 20 0 0 0 0 0 0 0 0 0 0 0 0 5 5 5 5 5 5 10 10 10 10 10 10 15 20 15 15 15 15 15 25 20 20 20 20 20 30 35 25 25 25 25 25 40 30 30 30 30 30 35 35 35 35 35 40 40 40 40 40 Time units t Time units t Time units t Time units t Time units t Time units t Simulation results and theoretical curves 21

Results – Graceful degradation Increase of the delay with rising defects 0.9 td [ns] Gate duplication 2.5 Gate duplication, overall power 0.9 0.8 0.7 0.6 Transistor duplication 0 1 2 3 Transistor duplication, overall power Number of defects Trend (gate duplication) 2.0 0.8 td [ns] Trend (transistor duplication) 1.5 P [mW] 1.0 0.7 0.5 0.6 0.0 0 10 20 30 0 5 10 15 20 Number of defects Number of defects 22

Results – Graceful degradation Increase of the overall power with rising defects due to increased static power consumption 2.5 Gate duplication, overall power Transistor duplication, overall power 2.0 Gate duplication, static power Transistor duplication, static power 1.5 P [mW] 1.0 0.5 0.0 0 5 10 15 20 Number of defects 23

Conclusion Need of design improvements for lifetime reliability Lowest abstraction level (transistor level) promises the most improvements concerning gate oxide breakdown Simpler integration of (as well good) gate level duplication into existing design flows and CAD tools Graceful degradation behavior in the presence of defects 24

Outlook Usage of more elaborate and complex breakdown models Additional implementation of devices with different gate oxide thickness Partial duplication of most vulnerable gates or transistors Investigation of the impact of soft breakdowns 25