Logic synthesis for post-CMOS technologies Eleonora Testa - PowerPoint PPT Presentation

Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory — EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017

Logic synthesis HDL module function ( Translate a, b, c, into gate level f); input a, b, c; output f; Optimization wire w0, w1, w2; & technology assign w0 = a & b; a assign w1 = a & c; mapping b assign w2 = w0 | w1; f assign f = w2; a endmodule b c c f a Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 2

Logic synthesis Optimization I Technology independent optimization 3 more strategies 7 not specific does not consider the technology I Technology aware optimization 3 better results 7 not general di ff erent for each technology Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 3

Technology aware optimization Emerging Technologies: CMOS Technologies: NAND/NOR-based 1 . di ff erent primitives VDD A B OUT 2 . technological constraints B A Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 4

Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 5

Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 6

Majority-based optimization QCA [1] SWD [2] MAJ INV MAJ INV Z ZN F F MAJ MAJ A B C IN A B C A [1] M. Houshmand et al. , Genetic Algorithm based Logic Optimization for Multi-Output Majority Gate- Based Nano-electronic Circuits. In ICIS, 2009. [2] O. Zografos et al. , Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, 2015. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 7

Majority-based optimization Internal resistance state Z n is a RRAM [3] function of the previous resistance state Z, the voltage at terminal P, and the voltage at Q Z n = h PQZ i Z n MAJ P Q Z [3] P.-E. Gaillardon et al. , The programmable logic-in-memory (PLiM) computer. In DATE, 2016. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 7

Majority-based optimization Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Majority-based optimization Majority logic: I h xyz i = xy _ xz _ yz = ( x _ y )( x _ z )( y _ z ) I h xy 0 i = x ^ y h xy 1 i = x _ y I Axiomatic system Ω . C : Commutativity h xyz i = h yxz i = h zyx i Ω . M : Majority h xxz i = x h x ¯ xz i = z Ω . A : Associativity h xu h yuz ii = h zu h yux ii Ω . D : Distributivity h xy h uvz ii = hh xyu ih xyv i z i Ω . I : Inverter propagation h ¯ x ¯ y ¯ z i = h xyz i Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Majority-based optimization I Data structure for Boolean functions based on majority logic: Majority-Inverter Graphs (MIGs) [4] L. Amarú et al. , Majority-Inverter Graph: A Novel Data-Structure and Algorithms for E ffi cient Logic Optimization. In DAC, 2014. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Majority-based optimization I Homogeneous logic network consisting of 3-input majority nodes and regular/complemented edges I Optimization of functions thanks to majority logic properties [5] f f MAJ MAJ Optimization 1 z MAJ z MAJ MAJ 1 y MAJ 1 y 1 w x z 1 w x [5] L. Amarú et al. , Boolean logic optimization in Majority-Inverter Graphs. In DAC, 2015. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Results: SWD I Majority enables SWD synthesis Benchmark ADPP SWD 10nm Ref. Impr. (x) 6 . 95 × 10 3 3 . 33 × 10 3 BKA264 0.48 1 . 53 × 10 4 4 . 53 × 10 4 HCA464 2.96 1 . 45 × 10 4 2 . 84 × 10 5 CSA464 19.51 5 . 69 × 10 4 2 . 26 × 10 6 DTM32 39.66 4 . 63 × 10 4 2 . 41 × 10 6 WTM32 52.04 4 . 14 × 10 3 2 . 79 × 10 7 DTM64 67.29 2 . 06 × 10 3 1 . 13 × 10 4 GFMUL 5.49 5 . 24 × 10 4 3 . 51 × 10 6 MAC32 67.00 3 . 13 × 10 5 2 . 51 × 10 8 DIV32 800.94 2 . 52 × 10 3 6 . 42 × 10 3 CRC32 2.55 9 . 24 × 10 4 2 . 87 × 10 7 Average 105.79 ADPP: Area-Delay-Power-Product, Impr: improvement. [2] O.Zografos et al. . Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, 2015. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 9

Results: RRAM I RRAM-based circuit benefits from MIG synthesis Benchmark naïve Rewriting and compilation # N # I # R # I Impr. # R Impr. adder 1020 2844 512 1911 32.81% 259 49.41% log2 32060 78885 1597 60184 23.71% 1256 21.35% max 2865 6731 1021 4996 25.78% 579 43.29% multiplier 27062 76156 2798 56009 26.45% 419 85.03% sin 5416 12479 438 10223 18.08% 402 8.22% sqrt 24618 60691 375 49782 17.97% 323 13.87% square 18484 54704 3272 33369 39.00% 452 86.19% P 236710 608655 22760 487214 19.95% 8785 61.40% # N : number of MIG nodes, # I : number of instructions, # R : number of RRAMs. [6] M. Soeken et al , An MIG-based compiler for programmable logic-in-memory architectures. In DAC, 2016. Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 10

Inversion minimization Ω . I : Inverter propagation h ¯ x ¯ y ¯ z i = h xyz i f = x � y � z f = x � y � z MAJ MAJ x x MAJ MAJ MAJ MAJ y y z x z x y y z x z x Inversion minimization 1. Tree based exact algorithm 2. SAT based exact algorithm 3. Heuristic algorithm by local rewriting Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 11

Results: QCA I QCA-based circuits benefit from inverter minimization Benchmark MIG Optimized MIG Impr. # N # L # E # INV # QCA cells # INV # QCA cells adder 2978 12 7452 1449 87754 830 85278 2.8% log2 37582 181 78917 22481 988087 8445 931943 5.7% max 7202 27 16186 3147 194272 1107 186112 4.2% multiplier 41885 111 92904 25594 1147937 12948 1097353 4.4% sin 7890 91 17275 3823 210217 1932 202653 3.6% sqrt 52344 690 111816 28734 1383000 12840 1319424 4.6% square 19200 36 39836 17158 523156 5012 474572 9.3% Average 4.9% # N : number of MIG nodes, # L : number of levels in the MIG not considering inverters, # E : number of edges, # INV : number of inverters, # QCA cells: number of QCA cells, Impr: improvement of the minimal values with respect to the initial MIG. [7] E. Testa et al. , Inverter Optimization in Majority-Inverter Graphs. In NANOARCH, 2016 Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 12

Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 13

Constraint-based logic synthesis Emerging Technologies: 2 . technological constraints Some examples I Limited number of outputs for each node = limited fan-out (e.g. optical devices) I Limited depth (e.g. quantum computing) I Inversion distribution (e.g. RRAMs) I More than one constraint (current work) Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 14

Constraint-based logic synthesis Emerging Technologies: 2 . technological constraints When considering constraints: Conventional approach a a Optimization b b & Optimization f f Constraints a a c c b ? c f a Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 14

Constraint-based logic synthesis Problem: Given some constraints and a Boolean function f , does there exist a circuit that can realize the function f within the given constraints? Constraint-solver SAT-solver 7 UNSAT 3 SAT b c f a Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 15

Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 16

Conclusions Constraint-based logic synthesis: Majority-based optimization: 3 fast 3 general approach and easily 3 abstract, applicable to a extensible variety of technology 3 exact solution 7 almost everything changes for each set of primitives 7 resource intensive, slow 7 requires new way of thinking 7 abstract Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 17

Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory — EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017