Why Again Logic Synthesis Giovanni De Micheli Why again logic - PowerPoint PPT Presentation

Why Again Logic Synthesis Giovanni De Micheli

Why again logic synthesis? § Strong intellectual value associated with logic synthesis and optimization § Problems are far from being solved § Current methods and tools grew out of control and random logic design for CMOS semicustom libraries § Still inefficient for computational engines with predominance of arithmetic units § Emerging nanotechnologies § New devices are game changers (c) Giovanni De Micheli 2

The emerging nano-technologies § Enhanced silicon CMOS is likely to remain the main manufacturing process in the medium term § The 10nm and 7nm technology nodes are on the way § What are the candidate technologies for the 5nm node and beyond? § Silicon Nanowires (SiNW) § Tunneling FETs (TFET) § Carbon Nanotubes (CNT) § 2D devices (flatronics) § What are the common denominators from a design standpoint? (c) Giovanni De Micheli 4

22 nm Tri-Gate transistors [Courtesy: M. Bohr] (c) Giovanni De Micheli 5

From FinFET to Nanowire FET FinFET NanoWire FET Three-sided gate Gate All Around 6

Electrostatic doping S CG D p-FET S CG D n-FET § Electrically program the transistor to either p-type or n-type § Field-effect control of the Schottky barrier 7

Silicon Nanowire Transistors § Gate all around transistors § Double gate to control polarity 8 [Courtesy: De Marchi, EPFL] (c) Giovanni De Micheli

Device I d /V cg ��������� Vds=2V ��������� �� Vpg = 0V Vcg Vpg = 2V �� Vpg Vpg = 4V �� Log( Id [A] ) �� �������� �� ��� �������� ��� ��� ��� ��� �� 0 � 2 3 4 Vcg [V] [Courtesy: De Marchi, IEDM 12 EPFL] 9

Logic level abstraction § Three terminal transistors are switches § A loaded transistor is an inverter § Controllable-polarity transistors compare two values § A loaded transistor is an exclusive or (EXOR) § The intrinsic higher computational expressiveness leads to more efficient data-path design § The larger number of terminals must be compensated by smart wiring (c) Giovanni De Micheli 10

Logic cell design § CMOS technology is efficient only for negative-unate functions § INV, NAND, NOR, AOI § Controllable-polarity logic is efficient for all functions § Best for XOR-dominated circuits (binate functions) Negative Unate functions Binate functions XOR2 NAND2 INV Gnd A B Gnd Gnd Y B Vdd Vdd A Vdd Only 4 transistors when compared to 8 Similar to regular CMOS transistors with a regular CMOS 11 (c) Giovanni De Micheli [Courtesy: H. Ben Jamaa, ’08]

Modular physical cell design Tile ¡ n1 n6 G1 G1 g1 g2 n2 n5 G2 G2 Two ¡transistor ¡pairs ¡ n3 n4 grouped ¡together ¡ NAND2 ¡ XOR2 ¡ (c) Giovanni De Micheli 12 [Courtesy: Bobba, DAC 12]

Modeling various emerging nanogates 4T Nanorelays CNFETs A B SiNWFETs 6T Nanorelays c 1 " c 1 " c 2 " c 2 " c n " c n " (c 1 "c 2 "…"c n )""""t" t" ⊕ Graphene FETs Reversible Logic (c) Giovanni De Micheli 13

Biconditional Binary Decision Diagrams § Native canonical data structure for logic design § Biconditional expansion: f ( v , w ,.., z ) = ( v ⊕ w ) f ( w ', w ,.., z ) + ( v ⊕ w ) f ( w , w ,.., z ) f(v,w,..,z) § Each BBDD node: § Has two branching variables § Implements the biconditional expansion PV=v § Reduces to Shannon’s expansion for SV=w single-input functions PV=SV PV=SV f(w’,w,..,z) f(w,w,..,z) [Courtesy: Amaru’, JETCAS 14] 14

BBDD: Examples a) b) c) d) f=(a ⊕ b)(b+c) f=a ⊕ b ⊕ c ⊕ d ⊕ e ⊕ g f=ab+(a ⊕ b)(c ⊕ d) f=ab+bc+ac a a a a b b b b = = = = = = = = b b b c 1 1 c d = = = = = = = = c c c e d 1 1 g = = = = = = = = 1 1 1 1 π = (a,b,c) π = (a,b,c) π = (a,b,c,d,e,g) π = (a,b,c,d) § The BDD counterparts for these examples have about 50% more nodes! 15

Efficient direct mapping of BBDD nodes BBDD MUX-XNOR f(v,w,..,z) f(v,w,..,z) v w v 0 1 w = = f(w’,w,..,z) f(w,w,..,z) f(w’,w,..,z) f(w,w,..,z) Transistor-level Implementation f(v,w,..,z) v w v w f(w’,w,..,z) f(w,w,..,z) v w v w 16 [Courtesy: Amaru’, DATE 13]

Compact BBDD representations S2 Cout a2 a2 b2 b2 3-bit adder = = = = b2 S1 0 1 a1 a1 § n-bit adder size: b1 b1 = = = = § 3n+1 nodes b1 S0 0 1 1 § BDD counterpart: a0 a0 b0 b0 § 5n+2 nodes = = = = b0 0 1 17 1

Compact BBDD representations MAJ7(a,b,c,d,e,f,g) g f 7-bit majority = = f MAJ5(a,b,c,d,e) e = = e e e § n-bit majority size: d d d = = = = = = § 0.25 (n 2 + 7) nodes d d d c c MAJ3(a,b,c) 0 1 = § BDD counterpart: = = = c c c ⌈ 0.5n ⌉ (n − ⌈ 0.5n ⌉ +1)+1 nodes § b b 0 1 = = = = b 1 0 a 1 0 1 18

The BBDD optimization tool § Recursive formulation of Boolean operations § Unique table to store BBDD nodes § Performance-oriented memory management § Chain variable reordering BBDD http://lsi.epfl.ch/BBDD Package BBDD (c) Giovanni De Micheli 19

Experimental results § We implemented a BBDD package in C language § Comparison with CUDD (BDD) § Both CUDD and BBDD first build the diagrams and then apply sifting 1.60E+04 Also 1.63x speedup for arithmetic 1.54e04 - 19.5% Node count 1.40E+04 intensive circuits 1.20E+04 1.00E+04 1.24e04 8.00E+03 CUDD BBDD (c) Giovanni De Micheli 20

Case study: arithmetic restructuring § Use BBDD to restructure arithmetic circuits prior to synthesis § Front-end to a commercial synthesis tool § Real-life telecommunication design: Iterative Product Code Decoder 21

Nanotechnology design § Iterative Product Code Decoder § Analysis after Physical Design: § 22 nm FINFET § 22-nm DG-SiNWFET [Courtesy: Amaru’, IEEE Proceedings 15] 22

Logic synthesis for design and assessment Technology evaluation Emerging technologies New tools Comparison to CMOS (c) Giovanni De Micheli 23

Conclusions § Emerging nano-technologies with enhanced-functionality devices increase computational density § New design, synthesis and verification methods stem from new abstractions of logic devices § Current logic synthesis is based on specific heuristics: new models with stronger properties lead us to better methods and tools for both CMOS and emerging devices 24 24

Thank you Never stop exploring !!! (c) Giovanni De Micheli 25