Lecture 15 Logistics HW6 is out, due Wednesday Last lecture - PDF document

Lecture 15 � Logistics � HW6 is out, due Wednesday � Last lecture � Continuing on basic building blocks for sequential logic � Latches and flip-flops � Clear/Preset � State Diagram � Asynchronous inputs � Today � Today � Continue more on building blocks for sequential logic � Timing issues with asynchronous inputs and some solutions � Registers � Summary of sequential logic building blocks CSE370, Lecture 17 15 1 Asynchronous inputs � Clocked circuits are synchronous � Unclocked circuits or signals are asynchronous � Unclocked circuits or signals are asynchronous � Synchronous circuits have asynchronous inputs � Reset signal, memory wait, user input, etc. � Inputs can change at any time � We must synchronize the input to our clock � Inputs can violate flip-flop setup/hold times CSE370, Lecture 17 15 2

Timing terminology and constraints � Setup time t su : Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) � Hold time t h : Amount of time the input must be stable after the � Hold time t h : Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF) � Clock width t w : Clock width that must be met � Propagation delays t plh and t phl : Propagation delay (high to low, low to high) (longer than hold time) t su t h t h t su D D Q Q t w CLK CLK Q t phl t plh CSE370, Lecture 17 15 3 Synchronizer failure � Occurs when input changes near clock edge � Input is neither 1 or 0 when clock goes high � Output may be neither 0 or 1 � Output may be neither 0 or 1 � May stay undefined for a long time � Undefined state is called metastability D CLK CLK Q logic 0 logic 1 CSE370, Lecture 17 15 4

Minimizing synchronizer failures � Failure probability can never be zero � Cascade two (or more) flip-flops � Effectively synchronizes twice � Effectively synchronizes twice � Both would have to fail for system to fail asynchronous synchronized D Q D Q input input Clk CSE370, Lecture 17 15 5 Cascading flip-flops � Flip-flop propagation delays exceed hold times � Second stage commits its input before input changes In IN Q1 Q0 D Q D Q t su t su Q0 > > t plh t phl Q1 Q1 CLK CLK Clk t h t h CSE370, Lecture 17 15 6

Side note: Clock skew � Goal: Clock all flip-flops at the same time � Difficult to achieve in high-speed systems � Clock delays (wire buffers) are comparable to logic delays � Clock delays (wire, buffers) are comparable to logic delays � Problem is called clock skew IN CLK0 clocks first flipflop Q0 CLK1 clocks second flipflop Q1 CLK1 should align with CLK0 CLK0, but is delayed CLK1 CLK1 due to clock skew Original state: IN = 0, Q0 = 1, Q1 = 1 Next state: Q0 = 0, Q1 = 0 (should be Q1 = 1) � Avoiding clock skew: design identical delays CSE370, Lecture 17 15 7 Handling asynchronous inputs � Never fan-out asynchronous inputs � Synchronize at circuit boundary � Fan-out synchronized signal � Fan-out synchronized signal Synchronizer Async Q0 Async Q0 D Q D Q D Q Input Input Clock Clock Q1 Q1 D Q D Q Clock Clock CSE370, Lecture 17 15 8

One more important concept: Debouncing � Switch inputs bounce � i. e. don’t make clean transitions � Can use SR latch for debouncing � Eliminates dynamic hazards � “Cleans-up” inputs 3.3V 0V R 1 Q 0 3 3V 3.3V 1 S Q' 0 3.3V 0V CSE370, Lecture 17 15 9 Summary: Timing issues with asynchronous inputs � For sequential logic circuits, timing issues have to be considered. � Inputs are often asynchronous and can cause problems. � Different amount of delay at different part of the circuit can cause problems also. � Solutions: � Cascade flip flops in series C d fli fl i i � Incorporate RS latch for debouncing � Design to keep timing alignment in mind (length of cable, etc) CSE370, Lecture 17 15 10

Registers � Group of storage elements read/written as a unit. � Store related values (e.g. a binary word) � Collection of flip-flops with common control � Share clock, reset, set lines � Example: � Storage registers � Shift registers � Counters CSE370, Lecture 17 15 11 Storage registers � Basic storage registers uses flip flops � Example: 4 bit storage register � Example: 4 bit storage register OUT1 OUT2 OUT3 OUT4 "0" R S R S R S R S D Q D Q D Q D Q CLK IN1 IN2 IN3 IN4 CSE370, Lecture 17 15 12

Shift registers � Hold successively sampled input values � Delays values in time � Example: 4-bit shift register � Example: 4-bit shift register � Stores 4 input values in sequence OUT1 OUT2 OUT3 OUT4 D Q Q D Q Q D Q Q D Q Q IN IN CLK CSE370, Lecture 17 15 13 Shift-register applications � Parallel-to-serial conversion for signal transmission serial transmission serial transmission parallel outputs CLK CLK parallel inputs � Pattern recognition (circuit recognizes 1001) OUT D Q D Q D Q D Q IN CLK CSE370, Lecture 17 15 14

Counters � Ring counter: Sequence is 1000, 0100, 0010, 0001 � Assuming one of these patterns is the starting state OUT1 OUT2 OUT3 OUT4 IN D Q D Q D Q D Q CLK � Johnson counter: Sequence is 1000, 1100, 1110, 1111 0111 0011 0001 0000 1111, 0111, 0011, 0001, 0000 OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK CSE370, Lecture 17 15 15 A binary counter � Has logic between flip-flops OUT1 OUT2 OUT3 OUT4 D1 D2 D3 D4 D Q D Q D Q D Q CLK "1” CSE370, Lecture 17 15 16

Summary: Sequential-logic building blocks � Know latches and flip-flops � Know clocks, timing, timing diagrams � Understand asynchronous inputs � Know basic registers CSE370, Lecture 17 15 17