Lecture 13 Logistics HW5 due Wednesday Last lecture Finished - PDF document

Lecture 13 � Logistics � HW5 due Wednesday � Last lecture � Finished combinational logic � Introduction to sequential logic and systems � Today � Finish the example from last time � Latches � Flip-flops Fli fl CSE370, Lecture 14 13 1 Example from last time: Combination lock � Door combination lock � Enter 3 numbers in sequence and the door opens � If there is an error the lock must be reset � After the door opens the lock must be reset � Inputs: Sequence of numbers, reset � Outputs: Door open/close � Memory: Must remember the combination CSE370, Lecture 14 13 2

State diagram and state table ERR closed not equal not equal & new not equal & new & new S1 S2 S3 OPEN closed closed closed reset open mux= C1 equal mux= C2 equal mux= C3 equal & new & new & new not new not new not new next next reset new equal state state mux open/closed 1 – – – S1 C1 closed 0 0 – S1 S1 C1 closed 0 1 0 S1 ERR – closed 0 1 1 S1 S2 C2 closed ... 0 1 1 S3 OPEN – open ... CSE370, Lecture 14 13 3 Combination lock system design new equal reset value C1 C2 C3 mux multiplexer controller control clock comparator equal equal open/closed open/closed CSE370, Lecture 14 13 4

Designing the datapath � Four 3:1 multiplexers � 2-input ANDs and 3-input OR value i C1 i C2 i C3 i � Four single-bit comparators � Four single bit comparators mux mux � 2-input XNORs control � 4-input AND C1 C2 C3 4 4 4 4 mux mux control multiplexer 4 value comparator equal equal 4 CSE370, Lecture 14 13 5 Designing the controller � We will learn how to special circuit element, design the controller called a register, for storing inputs when storing inputs when given the encoded i th d d told to by the clock state-transition table new equal reset mux comb. logic control control state clock open/closed CSE370, Lecture 14 13 6

Now we will learn how to store things! � First, we will learn several different logic elements (like how you had to learn AND and OR before you could d do functional things) f ti l thi ) � D latch � D flip flop � T flip flop � SR latch � Be patient --- once you know these components, you can do a lot in combinational logic! CSE370, Lecture 14 13 7 The D latch � Output depends on clock Input D Q Output � Clock high: Input passes to output Q Q Output Output � Clock low: Latch holds its output � Clock low: Latch holds its output � Latch are level sensitive and CLK transparent CLK D Q latch CSE370, Lecture 14 13 8

How do we make a latch? � Two inverters hold a bit � As long as power is applied "1" "0" "stored bit" � Storing a new memory � Temporarily break the feedback path "remember" "load" "stored bit" "data" CSE370, Lecture 14 13 9 The D flip-flop � Input sampled at clock edge Input D Q Output � Rising edge: Input passes to output Q Q Output Output � Otherwise: Flip-flop holds its output � Otherwise: Flip-flop holds its output � Flip-flops are rising-edge triggered, CLK falling-edge triggered, or master-slave CLK D Q ff CSE370, Lecture 14 13 10

How do we make a D flip flop? � Edge triggering is difficult W � You can do this at home: X � Label the internal nodes � Draw a timing diagram Q � Start with Clk= 1 Clk Q’ Y Y Z D CSE370, Lecture 14 13 11 Terminology & notation Rising-edge triggered Positive D latch D flip-flop Input D Q Output Input D Q Output Q Q Output Output CLK CLK Falling-edge triggered D flip-flop p p Negative D latch Input D Q Output Input D Q Output Q Q Output Output CLK CLK CSE370, Lecture 14 13 12

Latches versus flip-flops D Q CLK Q D CLK Q ff D Q Q Q latch CLK behavior is the same unless input changes while the clock is high CSE370, Lecture 14 13 13 T flip-flop � Full name: Toggle flip-flop � Output toggles when input is asserted � Output toggles when input is asserted � If T= 1, then Q → Q' when CLK ↑ � If T= 0, then Q → Q when CLK ↑ Input( t ) Q( t ) Q( t + Δ t ) Input Q T Q 0 0 0 0 0 0 > 0 1 1 1 0 1 CLK 1 1 0 CSE370, Lecture 14 13 14

The SR latch � Cross-coupled NOR gates � Can set (S= 1, R= 0) or reset (R= 1, S= 0) the output R Q Reset R Q S Q Set Q' S CSE370, Lecture 14 13 15 SR latch behavior � Truth table and timing S R Q 0 0 0 0 hold hold R R Q Q 0 1 0 1 0 1 1 1 disallow Q' S Hold Race Reset Set Reset Set 100 R R S Q Q' CSE370, Lecture 14 13 16

SR latch is glitch sensitive � Static 0 hazards can set/reset latch � Glitch on S input sets latch � Glitch on R input resets latch � Glitch on R input resets latch R 0 Q S Q' 0 CSE370, Lecture 14 13 17