Electronic devices fabrication (1)
IC… … wafer…
… and looking closer… ... and even closer
Material: Silicon Technology: planar (epitaxial) Why silicon (wrt. Ge)? - excellent oxide (SiO 2 ) - it’s a mask for dopants - excellent dielectric material (for MOSFET gates and as insulator) - relatively easy processing - wider gap -> less sensitive to T * however, V CEsa t is large and carrier mobility is lower
Planar epitax. technology: how a junction is built
Short review (anticipation?) on … PN junction inverse saturation current ~ nA breakdown parasitic capacitances BJT C: low doping (to have large V br ) B: narrow/short (for speed and gain) E: high doping (to have “good” carriers)
BJT + + + - junction isolation -> n - tank (tub) -> parasitic C - buried n + layer (to have low R coll ) - n + for C (to avoid Schottky)
More components together...
CMOS (e.g.: N-well process, poly gate, double metal) (well, there is an error... where?)
The first IC [Jack Kilby, 1959]…
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