Design of Complex Stochastic Systems: Semiconductor Wafer Fabrication and Port Services James R. Morrison KAIST, Department of Industrial and Systems Engineering xS3D Lab Students: Seunghwan Jung, Jonghoe Kim, Minsung Kim and Kyungsu Park 2 nd KI International Symposium, September 4 - 9, 2008
Presentation Overview • Part I: Design of stochastic systems • System description: Photolithography clusters in computer chip fabrication • Why does a system-level and stochastic perspective matter? • Design for throughput • Part II: Design of service systems • Port system decoupling leads to service concept • Concluding remarks 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 2
System Description: Photolithography (1) • Semiconductor wafer/LCD fabrication are key industries • 2007 worldwide revenue: W270x10 9 (US$270 billion) • 2007 Samsung Electronics revenue: W21x10 9 (US$21 billion) • 2007 Korean GDP: ~ W1,000x10 9 (US$ 1 trillion) • State-of-the-art fabricator construction: ~ US$3 billion • Photolithography cluster tools • Key toolset in semiconductor wafer fabrication • Typically a fabricator bottleneck (even with dozens of tools) • Cost: ~ W20x10 9 (US$20 million) [1] Gartner Research, http://www.gartner.com, [2] CIA World Fact Book [3] EE Times Asia, http://www.eetasia.com, 2007/07/20, [4] Scanner image courtesy of ASML 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 3
System Description: Photolithography (2) • Operation of a of photolithography cluster tool • Process modules coat each wafer with photosensitive films • Photolithography scanner exposes the film to a light pattern • Process modules develop the image on the film Wafer path for coating Scan Wafer path for develop 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 4
System Description: Photolithography (3) m A m B m A m B m C m 1 m 4 2 2 3 3 3 m 5 m B m A m C m B m A m B m A 8 8 7 7 7 6 6 • Several modules may be devoted to a single process • Scanner will be the system bottleneck (least throughput potential) • Process time for wafer j in module m i is a constant t j i • Wafers of different kinds may require different process times • May have a buffer before the bottleneck (scanner) 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 5
System Description: Photolithography (4) • Design question: When should the robots advance the wafers? • Design of steady-state operation • Axiomatic design has shown that periodic operation is a good design 1 • Cyclic (periodic) robot schedule is throughput optimal 2 • Design of transient operation? • Transients are generally ignored, and if not… • Typical objective is to reestablish steady state operation [1] Hilario L. Oh and Tae-Sik Lee, “A synchronous algorithm to reduce complexity in wafer flow,” Proceedings of the 1 st International Conference on Axiomatic Design (ICAD), pp. 87-92, June 21-23, 2000. [2] M. Dawande, N. Geismar and S. Sethi , “Dominance of cyclic solutions and some open problems in scheduling bufferless robotic cells,” SIAM Review, vol. 47, pp. 207 -721, 2005. 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 6
System-Level Perspective (1) • Good steady-state design ensures maximum throughput potential (this is what the tool supplier quotes as speed) • In practice: • Modules may require a setup between different types of wafers • Modules conduct self-cleaning operations • Photolithography scanner pauses production when settings change • Tool must be emptied before maintenance and filled after • Production may wait while monitor (test) wafers are run • These events may be considered to occur randomly 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 7
System-Level Perspective (2) Throughput Potential and Non Steady-State Phenomenon Ideal steady 80 wph state Wafers Per Hour Return from Non steady-state 69 wph maintenance events cause Module clean 61 wph dramatic loss! and monitor Wafer to 55 wph wafer interactions Actual throughput Actual throughput x 1.45 = Ideal throughput 0 wph [1] James R. Morrison, Beverly Bortnick and Donald P. Martin, “Performance evaluation of serial photolithography clusters: Queueing models, throughput and workload sequencing,” Proceedings of the 2006 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Boston, MA, pp. 44-49, May 2006. *2+ James R. Morrison and Donald P. Martin, “Performance evaluation of photolithography cluster tools: Queueing and throughput models,” OR Spectrum (Springer) , Vol. 29, No. 3, pp. 375-389, July 2007. 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 8
Axiomatic Design at the System Level (1) • Goal: • Design photolithography cluster tool • Take a system-level approach (explicitly address non steady-state) • Constraints: • Module process times are known and fixed (t j i ) – scanner is bottleneck • Buffer modules may be placed only just before the bottleneck (scanner) • Setups may be required between wafers of different types • Wafer may have a maximum allowed residency time in each module ( time window: [t j i , t j i + r j i ] ) – process is a success if this is obeyed • Objective(s): • Maximize steady-state throughput • Minimize the effect of disturbances on throughput (“non steady - state”) • Minimize variation in module residence times for like wafers 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 9
Axiomatic Design at the System Level (2) Functional Requirements: Design Parameters: • FR1. Conduct wafer processes • DP1. Process modules to exceed bottleneck rate ( l B ) • FR2. Transport wafers • DP2. Robots and algorithms (physically + orchestration) FR 1 X 0 DP 1 So long as our robots/algorithms obey the FR 2 X X DP 2 process time windows, this will remain 0! X = Relationship between DP and FR Decoupled design 0 = Negligible relation between DP and FR [1] Axiomatic Design: Advances and Applications, Nam Pyo Suh, Oxford University Press, 2001 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 10
Axiomatic Design at the System Level (3) Functional Requirements: Design Parameters: • FR1.1. Position, enter/exit wafers • DP1.1. Method for positioning • FR1.2. Conduct process • DP1.2. System for processing • FR1.2.1. Prepare for process • DP1.2.1. Recipe setup system • FR1.2.2. Maintain process quality • FR1.2.2. Module cleaning system • FR1.2.3. Conduct process • FR1.2.3. Process modules • FR1.2.4. Ensure process rate (< l B ) • FR1.2.4. Sufficient number of modules • FR2.1. Physically move wafers • DP2.1. Robots • FR2.2. Orchestrate steady state • DP2.2. Algorithms for steady state (SS) operation (SS) operation • FR2.2.1. Decouple SS process times • DP2.2.1. Cyclic schedule • FR2.2.2. Minimize SS wait to transport • DP2.2.2. Algorithm to minimize waiting • FR2.3. Orchestrate transient • DP2.3. Algorithms/structure for operation transient operation 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 11
Axiomatic Design at the System Level (4) Functional Requirements: Design Parameters: • FR 2.3. Orchestrate transient • DP 2.3. Algorithms/structure for operation transient operation • • FR2.3.1. Reestablish SS DP2.3.1. Algorithm to return to SS • • FR2.3.2. Protect from disturbance DP2.3.2. Buffer before the bottleneck • • FR2.3.3. Recover time lost due to DP2.3.3. Algorithm to minimize distance disturbance between normal/disturbed wafers • • FR2.3.4. Maintain decoupling for DP2.3.4. Same SS cyclic schedule for wafers not delayed by disturbance wafers not disturbed • • FR2.3.5. Decouple and minimize DP2.3.5. Algorithm to decouple and transient wafer residency times minimize delayed wafers • • FR2.3.6. Replenish protection from DP2.3.6. Wafer input rate to tool delay (= process rate of prescan bottleneck) 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 12
Axiomatic Design at the System Level (5) • Concepts of the design (design parameters) DP2.3.3. Minimum distance between delayed/normal wafers DP2.3.6. Input rate DP2.3.2. Buffer DP2.3.5. Decouple Scan transient transport DP2.3.4. Same SS cyclic schedule for wafers downstream of(after) disturbance DP2.3.1. Algorithm to return all wafers to SS cyclic schedule 2 nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 13
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