and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH - PowerPoint PPT Presentation

Wafer-Level Packaging and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH Workshop 6 Portland OR Patty Chang-Chien Northrop Grumman Aerospace Systems

Acknowledgement • Multi-center effort at NGAS: Microelectronics, RF Product Center, Manufacturing, Product Engineering, Materials, Antenna Product • Kelly Hennig, Xiang Zeng, David Eaves, Phil Hon, Peter Chou, Gerry Mei, Roger Tsai, David Farkas, John Chen, Keang Kho, Mike Battung, Yun Chung, Pei-Lan Hsu, Jeff Yang, Wendy Lee, Matt Nishimoto, Tony Long, Greg Rowan, Sean Shih, Dah-Weih Duan, Jose Padilla, Pin-Pin Huang, Minhdao Truong, Richard To, K.K. Loi, Hui Ma, Jeremy Ou-Yang, Craig Geiger, Gershon Akerling, Chi Cheung, Sujane Wang, Jane Lee, Danny Li, Peter Nam, Peter Ngo, Martin IIyama, Ging Wang, Tom Chung, Gary Gurling, Randy Duprey, Cesar Romo, Ben Heying, Randy Sandhu, Ben Poust, Matt Parlee, Denise Leung, David Eng, Eric Kaneshiro, Rich Kono, Jansen Uyeda, Mike Barsky, Jennifer Gan, Ke Luo, Fred Dai, Edna Yamada, Mike Wojtowicz, Rich Lai, Augusto Gutierrez, Aaron Oki and many more! 2

Agenda • Overview – Technology description – Benefits • 2-Layer WLP/WSA – Process description – Examples • Interconnects & Transitions • Package Performance • Multi-Layer WLP/WSA – Process description – Examples • Higher Order Integration 3

What is Wafer-Level-Packaging? Wafer-Level Packaging (WLP) AKA: Micro Packaging AKA: Wafer-Scale Assemlby (WSA) State-of-the-art MMIC Wafer 3-D Wafer Scale Assembled IC • Add inter-cavity interconnects and cavity ring • Stack and bond multiple wafers, then dice • Forms a hermetically packaged 3-D integrated circuit • Enables integration of different MMIC technologies WLP provides low cost, high volume, hermetic packaging 4

Advanced Capabilities for Next-Generation Systems • Next-generation system needs performance superiority & affordability • WLP performance superiority Large Aperture – Advanced integration Phased Arrays • best semiconductor technology for the function – Ultra-compact, light weight packaging • size & weight savings – High functional density & low loss interconnects • Superior circuit performance – Hermetic MMIC packaging Military Systems • Enhanced circuit reliability • WLP Affordability – Batch fabrication processes • Low cost, high volume – Fully compatible with NGAS MMIC production processes Restricted Satellite Comm. • Existing & proven MMIC technologies • Next-generation MMIC technologies – Reduce higher order assembly cost, relax module assembly requirement 5

WLP Benefits Heterogeneous • Superiority Integration using WLP – Hermetic compact MMIC packaging – Performance enabler • High functional density • Superior circuit performance • Affordability Combine multiple MMIC wafers by wafer bonding technology – Batch fabrication processes, low cost, high volume – Reduce higher order assembly cost, relax module assembly requirement Integrated Wafer-Level- Microwave Package (WLP) Assembly (IMA) Size reduction 1 1,000X Tri-layer WLP TR Module X-band operation Weight reduction 1 1,000X Mass: <15mg Cost reduction 1 10-100X Size: 2.5mm x 2mm x 0.46mm WLP content: 3 bit PS, LNA, PA WLP offers superiority in performance and affordability in cost 6

Integrated Microwave Assembly Packaging GaAs GaN CMOS InP IMA 7

Wafer-Level Integration Benefits • Hermetic • Ultra-light weight, ultra-compact • Low cost, high volume • Performance enhancement IMAs Weight: g to >1000g Size: cm x cm x cm Assembly: serial, manual Package near a thumb tack Wafer-Level Integrated Package Weight: < 50 mg Size: mm x mm x mm Assembly: mass parallel, wafer scale 8

Integration Using Wafer-Level Packaging • WLP is assembled using a low temperature wafer bonding process • WLP technology is fully compatible with NGAS MMIC production processes Through Bonding Via Ring Circuit with Wafer Bonding Ring (wafer 1) Wafer Bonding Bonding Ring Circuit (wafer 2) (low-noise amplifier) Low temperature wafer bonding process is key to MMIC compatible, robust WLP 9 –10 –20 –30 –40

2-LAYER WLP 10

2-Layer WLP • Wafers are individually processed prior to bonding – No changes to standard MMIC processes 2-layer Bonding Process Flow • ICIC = Intra-Cavity InterConnections ICIC ICIC • BICIC = Backside ICIC Wafer 2 Wafer 2 Wafer 1 Wafer 1 2-layer Bonding Process Flow BICIC BICIC Flip & align Flip & align Wafer Bonding Wafer Bonding ICIC (Front side) ICIC (Front side) BICIC (backside) BICIC (backside) Bonding Layer Bonding Layer Bonded pair Bonded pair Bonded pair 2-Layer WLP is constructed by bonding 2 individually processed wafers 11

WLP Demonstrations • WLP is fully compatible with NGAS’s MMIC production processes Substrate combinations w/ WLP Frequency bands w/ WLP • GaAs + GaAs • X-band Ka-band • InP + GaAs • InP + InP • Ku-band Q-band • Quartz + Quartz • V-band W-band • Si + InP • Glass + Glass • GaAs + Duroid Different circuit types w/ WLP • GaAs + InP + GaAs • LNAs PAs • GaAs + InP + InP • SiC + SiC • Oscillators Phase shifters • Multiple GaAs integrations • Shift registers Switches • Multiple InP integrations Different compound-semiconductor technologies w/ WLP InP HEMTs InP HBTs ABCS HEMT GaAs HEMTs MEMS switches GaAs HBTs Passives GaAs Schottky diodes GaN HEMTs InP diodes NGAS has extensive experience in heterogeneous integration using WLP 12

Examples of Packaged MMICs Ku Band LNA, WLP GaAs HEMT circuit Ku Band LNA, WLP GaAs HEMT circuit Ku Band PA, WLP GaAs HEMT circuit 25 30 30 25 25 20 20 20 S21 (dB) S21 (dB) S21 (dB) 15 15 15 10 10 10 5 5 5 0 0 0 0 0 5 5 10 10 15 15 20 20 25 25 5 10 15 20 25 Frequency (GHz) Frequency (GHz) Frequency (GHz) W-Band PA, WLP GaAs HEMT circuit W-Band PA, WLP GaAs HEMT circuit WLP Q-Band LNA (IRFFE) Q-Band LNA, WLP GaAs HEMT Circuit 16 16 20 14 14 12 12 10 10 10 S21 (dB) S21 (dB) 0 S21 (dB) LNA LNA 8 8 -10 6 6 -20 4 4 Bonding Ring Bonding Ring -30 2 2 0 0 -40 80 80 85 85 90 90 95 95 100 100 105 105 110 110 0 10 20 30 40 50 Frequency (GHz) Frequency (GHz) Frequency (GHz) 13

Wafer Level Packaging (WLP) MMICs Proven across the bands 4-bit PHSH -Chip size: x=3.3mm, y=2.7mm -TTL compatible -avg RMS Amp Error=1.08dB -avg RMS Phase Error=16.5º 2-Stage, self-biased LNA -Chip size: x=3.3mm, y=2.7mm -bias: 4V, 26 mA -Gain > 26.5 dB at 16 GHz 2-Stage PA 3-Stage, self-biased LNA 3-Stage, self-biased LNA -Chip size: x=3.3mm, y=2.7mm -Chip size: x=4.2mm, y=4.2mm -Chip size: x=4.2mm, y=4.2mm -bias: 4V, 120 mA -bias: 4V, 60 mA -bias: 4V, 45 mA -Gain > 19 dB at 16 GHz -Gain > 11.8 dB from 30-50 GHz -Gain > 24 dB at 35 GHz KA Q KU Miniaturized WLP T/R modules for large arrays 14

GaN WLP Technology • Developed world’s first GaN wafer level package process for record power density • Demonstrated >99% GaN WLP interconnect yield Passive Cover Wafer Active GaN Wafer Photo of GaN WLP MMIC GaN WLP chip GaN WLP TEG chip 15

W-Band WSA Oscillator • W-Band oscillator with built-in on chip resonant cavity • 2-layer active MMIC integration: – InP HEMT + GaAs HBT Measured spectrum of Oscillator Photo of the integrated oscillator chip 1 st and 2 nd Half of 1 st and 2 nd Half of Coupling Coupling Through Wafer Through Wafer Active Device Active Device Through Wafer RF Transition Through Wafer RF Transition Resonant Cavity Resonant Cavity Slot Slot RF Transition RF Transition (Backside Probe Location) (Backside Probe Location) Demonstrated 2-Layer WSA Oscillator 16

Comparison of WLP and non-WLP circuits ALH 140 ALH140 vs. ALH140V3 ALH140_1 ALH140_2 1.4mm ALH140_3 18 ALH140_4 ALH140_5 16 ALH140_6 ALH140_7 14 ALH140_8 ALH140_9 12 ALH140_10 2.5mm ALH140_11 S21 (dB) ALH140_12 10 ALH 140V3 (WLP) ALH140_V3_1 : Conventional ALH140 ALH140_V3_2 8 ALH140_V3_3 (FIDR1/A-J103 1146A-031) ALH140_V3_4 6 ALH140_V3_5 : ALH140V3 with WLP cover ALH140_V3_6 (WLP5/1/P200-001) 1.9mm ALH140_V3_7 4 ALH140_V3_8 ALH140_V3_9 2 ALH140_V3_10 ALH140_V3_11 0 ALH140_V3_12 30 31 32 33 34 35 36 37 38 39 40 Frequency (GHz) 3.2mm RF performance similar for WLP and non-WLP circuits 17

2-LAYER INTEGRATED WLP/WSA EXAMPLES 18

Heterogeneous Integration Example • Integrated RF front end module with antenna – Amplifier (GaAs HEMT) – 3 bit phase shifter (GaAs HEMT) – Interconnections (ICICs) – Antenna WLP bottom side WLP top side (antenna) Integrated RF Front-End Module Sealing Ring Sealing Ring (Wafer 2) (Wafer 2) Wafer 1 antenna antenna Wafer 2 Wafer 2 Sealing Ring Sealing Ring Wafer Wafer (Wafer 1) (Wafer 1) ICIC ICIC Bonding Bonding Amplifier Amplifier Phase Phase Wafer 1 Wafer 1 shifter shifter Through wafer via Through wafer via Ground Fence Ground Fence 19

On-Wafer Measured Data • WLP technology - Wafer1=passive, 4-mil GaAs - Wafer2=0.1um, 4-mil GaAs • 2-stage balanced Amplifier • 3-bit reflective phase shifter Phase Shifter Phase States Amplifier S-Parameter 20 400 Magnitude (dB) S21 Phase (deg) 300 0 S11 200 -20 S22 100 -40 0 10 20 30 40 50 1 2 3 4 5 6 7 8 Frequency (GHz) Phase States 20