3D I ntegration Using Wafer-Level Packaging July 21, 2008 Patty Chang-Chien MMIC Array Receivers & Spectrographs Workshop Pasadena, CA
Agenda • Wafer-Level Packaging Technology Overview • IRAD development on large arrays • Advanced Integration • Next Level Assembly • Summary / Future work 2
What is Wafer-Level-Packaging? Wafer-Level Packaging AKA: Micro Packaging AKA: Wafer-Scale Assemlby (WSA) State-of-the-art MMIC Wafer 3-D Wafer Scale Assembled IC • Add inter-cavity interconnects and cavity ring • Stack and bond multiple wafers, then dice • Forms a hermetically packaged 3-D integrated circuit • Enables integration of different MMIC technologies WLP provides low cost, high volume, hermetic packaging WLP provides low cost, high volume, hermetic packaging 3
Integrated Microwave Assembly Packaging GaAs GaN CMOS InP IMA 4
Wafer-Level Integration Benefits • Hermetic • Ultra-light weight, ultra-compact • Low cost, high volume • Performance enhancement IMAs Weight: g to >1000g Size: cm x cm x cm Assembly: serial, manual Package near a thumb tack Wafer-Level Integrated Package Weight: < 50 mg Size: mm x mm x mm Assembly: mass parallel, wafer scale 5
Superiority And Affordability • Superiority – Hermetic packaging in compact form factor • Protect MMICs against harsh environment • Enhance circuit reliability Integrated Microwave Wafer-Level- Factors of – Superb circuit performance Assembly Package (WLP) Improvement (IMA) • Good circuit isolation 1/1000 & ⇓ Size 1 • Low transition loss • Low parasitics: eliminate wire bonds 1/1000 & ⇓ Weight 1 > 100,000,000 – High functional density 1/100 & ⇓ Cost 1 • One package replaces many MMICs • Ultra compact, ultra light weight • Relax system requirement: decrease # of modules required, simple drive scheme • Affordability – Batch fabrication processes, low cost, high volume – Reduce higher order assembly cost, relax module assembly requirement Heterogeneous Integration Offers Superiority Heterogeneous Integration Offers Superiority in Performance and Affordability in Cost in Performance and Affordability in Cost 6
2-Layer WLP • Wafers are individually processed prior to bonding – No changes to standard MMIC processes 2-layer Bonding Process Flow • ICIC = Intra-Cavity InterConnections ICIC ICIC Wafer 2 Wafer 2 Wafer 1 Wafer 1 • BICIC = Backside ICIC 2-layer Bonding Process Flow BICIC BICIC Flip & align Flip & align Wafer Bonding Wafer Bonding ICIC (Front side) ICIC (Front side) BICIC (backside) BICIC (backside) Bonding Layer Bonding Layer Bonded pair Bonded pair Bonded pair 2- -Layer WLP is Constructed by Layer WLP is Constructed by 2 Bonding 2 Individually Processed Wafers Bonding 2 Individually Processed Wafers 7
Integration Using Wafer-Level Packaging • WLP is assembled using a low temperature wafer bonding process • WLP technology is fully compatible with NGST MMIC production processes Through Bonding Via Ring Circuit with Wafer Bonding Ring (wafer 1) Wafer Bonding Bonding Ring Circuit (wafer 2) (low-noise amplifier) Low temperature w afer bonding process is Low temperature w afer bonding process is key to MMIC compatible, robust WLP key to MMIC compatible, robust WLP 8
Examples of Packaged MMICs Ku Band LNA, WLP GaAs HEMT circuit Ku Band LNA, WLP GaAs HEMT circuit Ku Band PA, WLP GaAs HEMT circuit 25 30 30 25 25 20 20 20 S21 (dB) S21 (dB) S21 (dB) 15 15 15 10 10 10 5 5 5 0 0 0 0 0 5 5 10 10 15 15 20 20 25 25 5 10 15 20 25 Frequency (GHz) Frequency (GHz) Frequency (GHz) W-Band PA, WLP GaAs HEMT circuit W-Band PA, WLP GaAs HEMT circuit WLP Q-Band LNA (IRFFE) Q-Band LNA, WLP GaAs HEMT Circuit 16 16 20 14 14 12 12 10 10 10 S21 (dB) S21 (dB) 0 S21 (dB) 8 8 LNA LNA -10 6 6 -20 4 4 Bonding Ring Bonding Ring -30 2 2 0 0 -40 80 80 85 85 90 90 95 95 100 100 105 105 110 110 0 10 20 30 40 50 Frequency (GHz) Frequency (GHz) Frequency (GHz) 9
Comparison of WLP and non-WLP circuits ALH 140 ALH140 vs. ALH140V3 ALH140_1 ALH140_2 1.4mm ALH140_3 18 ALH140_4 ALH140_5 16 ALH140_6 ALH140_7 14 ALH140_8 ALH140_9 12 ALH140_10 2.5mm ALH140_11 S21 (dB ) ALH140_12 10 ALH 140V3 (WLP) ALH140_V3_1 ALH140_V3_2 : Conventional ALH140 8 ALH140_V3_3 (FIDR1/A-J103 1146A-031) ALH140_V3_4 6 ALH140_V3_5 : ALH140V3 with WLP cover ALH140_V3_6 (WLP5/1/P200-001) ALH140_V3_7 1.9mm 4 ALH140_V3_8 ALH140_V3_9 2 ALH140_V3_10 ALH140_V3_11 0 ALH140_V3_12 30 31 32 33 34 35 36 37 38 39 40 Frequency (GHz) 3.2mm RF performance similar for WLP and non-WLP circuits 10
Converting Existing Chips to WLP • Almost all existing chips can be converted into a WLP chip with a passive cover • Layout changes are straightforward • RF performance of converted chip will change depending on chip sensitivity, performance, and frequency • Simulations may need to be performed to assess RF performance changes due to WLP cavity • WLP conversion will generally increase the size of the chip 11
Heterogeneous Integration Example • Integrated RF front end module with antenna – PA (GaAs HEMT) – 3 bit phase shifter (GaAs HEMT) – Interconnections (ICICs) – Antenna WLP bottom side WLP top side (antenna) Integrated RF Front-End Module Sealing Ring Sealing Ring (Wafer 2) (Wafer 2) Wafer 1 antenna antenna Wafer 2 Wafer 2 Sealing Ring Sealing Ring Wafer Wafer (Wafer 1) (Wafer 1) ICIC ICIC Bonding Bonding Amplifier Amplifier Phase Phase Wafer 1 Wafer 1 shifter shifter Through wafer via Through wafer via Ground Fence Ground Fence 12
WLP Linear Array Demonstration Measured Beam Pattern • Demonstrated fully functional front-end 0 modules with a linear 4-element array -5 θ = 0 ° – GaAs HEMT + passive -10 – LNA + 3bit PS + antenna in an integrated E-Field Magnitude (dB) -15 Q-Band WLP package – Successful integration to BFN board -20 – Demonstrated electronic beam steering -25 θ =15 ° -30 -35 -40 -60 -40 -20 0 20 40 60 Integrated RF front-end modules w/ antenna θ (deg) WLP bottom side WLP top side Beam Forming Network (board) (antenna) 13
WLP Demonstrations • WLP is fully compatible with NGST’s MMIC production processes • Demonstrations to-date – Different compound-semiconductor technologies – Different circuit types w/ WLP w/ WLP • LNAs • InP HEMTs • PAs • GaAs HEMTs • Oscillators • Phase shifters • GaAs HBTs • Shift registers • GaAs Schottky diodes – Substrate combinations w/ WLP • InP HBTs • GaAs + GaAs • ABCS HEMT • InP + GaAs • MEMS switches • InP + InP • Passive components • Quartz + Quartz – Frequency bands w/ WLP • Si + InP • X-band • Glass + Glass • Ka-band • GaAs x 3 • Q-band • GaAs x 4 • GaAs x 5 • Ku-band • GaAs + Duroid • V-band • GaAs + InP + GaAs • W-band NGST has extensive experience in heterogeneous integration using WLP 14
Package Integrity • WLP packages passed the following tests: • Vibration-Sine – MIL-STD 883F, Method 2007.3, condition B • Mechanical Shock (Pyroshock) – MIL-STD 883F, Method 2002.4, condition B • Temperature Cycling – MIL-STD 883F, Method 1010.8, condition B – -55º C to 125º C, 50 cycles, MEMS – -55º C to 85º C, 300+ cycles, W-Band GaAs circuits • Hermeticity – MIL-STD 883F, Method 1014.11 – He fine leak, condition A2, flexible – Radioisotope fine leak, condition B – Penetrate dye gross leak, condition D • Die Shear – MIL-STD 883F, method 2019.7 • Environmental test: 85C 85% humidity 7 days Ku band GaAs MMICs WLP packages are hermetic, thermally WLP packages are hermetic, thermally and mechanically robust and mechanically robust 15
Advanced Integration: Multiple Layer WLP 4-layer Bonding Process Flow • 4-layer construction Bonded Pair 1 Bonded Pair 2 – Use bonded pair as starting units Multiple Layer WSA Flow Multiple Layer WSA Flow Bonded Pair 2 Bonded Pair 2 Bonded Pair 1 Bonded Pair 1 or single wafer or single wafer Process Bonding Process Bonding layer if necessary layer if necessary (backside) (backside) ICIC (Front side) ICIC (Front side) BICIC (backside) BICIC (backside) Bonding Layer Bonding Layer Wafer Bonding Wafer Bonding 4- -Layer Construction is Achieved By Layer Construction is Achieved By 4 Bonding 2 bonded WLP pairs Bonding 2 bonded WLP pairs 16
X-Band Tri-Layer Tx/Rx Modules ABCS HEMT LNA WLP Tx/Rx Module Average mass: 12.9mg Size: 2.5mm x 2mm x 0.46mm • Next-Generation Large Aperture InP HBT PA & digital control Array T/R Module – Ultra light weight (<15 mg) – Extremely compact (<5 mm 2 ) • Transceiver Module Performance h h c c Goal t t i i w w S S – FOM > 10,000 – Reliability: MTTF >10 6 Hours GaAs HEMT PS & Switches Demonstrated X - -Band Integrated T/R Module Band Integrated T/R Module Demonstrated X 17
Microbump: Chip-Board Integration Cu stud microbump • Developed microbump technologies for WLP– to-board attachment and integration Microbumps on backside of the package Sn/Pb microbump array Microbumps Enable WLP Enable WLP- -to to- -Board Integration Board Integration Microbumps 18
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