CMOS Comparator Design Extra Slides Vishal Saxena, Boise State - PowerPoint PPT Presentation

Department of Electrical and Computer Engineering CMOS Comparator Design Extra Slides Vishal Saxena, Boise State University (vishalsaxena@boisestate.edu) Vishal Saxena -1-

Comparator Design Considerations Comparator =   Preamp (optional)  + Reference Subtraction (optional for single-bit case)  + Regenerative Latch  +Static Latch to hold outputs (optional) Design Considerations   Accuracy (dynamic and static offset, noise, resolution)  Settling time (tracking BW, regeneration speed)  Sensitivity/resolution (gain)  Metastability (ability to make correct decisions)  Overdrive recovery (memory)  Power consumption Vishal Saxena -2-

An Example CMOS Comparator V os orginiates from: V DD • Preamp input pair mismatch (V th ,W/L) M 3 M 4 M 5 M 6 • PMOS loads and Φ V os current mirror + - V o V o M 1 M 2 • Latch offset V i M 9 • Charge-Injection M 7 M 8 clock-feedthru imbalance of the reset switch (M9) V SS • Clock routing Preamp Latch • Parasitics Vishal Saxena -3-

Latch Regeneration V DD PA tracking Latch Φ Latch reseting regenrating M 5 M 6 Φ V DD + - V o V o + V o M 9 C L C L V o M 7 M 8 - V o V SS V SS • Exponential regeneration due to positive feedback of M 7 and M 8 Vishal Saxena -4-

Regeneration Speed – Linear Model + + - V o V o V o -1  C L C L - C L g m V o - V o M 7 M 8            V V 1 1 V       o o  o 0             1 g /sC   V   V g V /sC m L o o m o L        Δ s g /sC 1 0 s g /C , single RHP pole m L p m L            V t 0 V t 0 exp t g /C o o m L Vishal Saxena -5-

Reg. Speed – Linear Model + - V o V o C L C L V o (t=0) t V o = 1V M 7 M 8 V o V o (t=0) t/(C L /g m ) 1V 100mV 2.3     C V t   L o t ln    1V 10mV 4.6   g  V t 0  m o 1V 1mV 6.9 100 μ V 1V 9.2 Vishal Saxena -6-

Reg. Speed – Linear Model Reg. Speed – Linear Model + - + - M 3 M 4 V m M 5 M 6 V m g m5 V m g m5 V m + - V m V m Φ =1 R 9 R 9  x + - + - V o V o V o V o 2 2 M 1 M 2 V i M 9 X -1 -1 M 7 M 8 g m7 g m7 g g R R 1    m1 m5 9 9 A A , to be amplifier. V1 V2  2 g R 2 g g m3 m7 9 m7           V 0 V 0 A V 0 A A o i V i V1 V2           V t V 0 A A exp t g /C o i V1 V2 m L Vishal Saxena -7-

Comparator Metastability Reg. Speed – Linear Model T/2           V t V 0 A A exp t g /C o i V1 V2 m L Φ Curve A V1 A V2 V i (t=0)  10 10 mV 1 2 3 4  10 1 mV + V o  100 μ V 10 - V o  10 μ V 10 Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold Vishal Saxena -8-

Comparator Metastability Reg. Speed – Linear Model D o Δ Assuming that the input is uniformly j+1 distributed over V FS , then Δ BER  V i 1 LSB j           V t V 0 A A exp t g /C o i V1 V2 m L V os • Cascade preamp stages (typical flash comparator has 2-3 pre-amp stages) • Use pipelined multi-stage latches; pre-amp can be pipelined too Vishal Saxena -9-

Charge-Injection and Clock-Feedthrough in Latch Reg. Speed – Linear Model Φ M 5 M 6 Φ + - V o V o C gs C gd CM M 9 jump C L C L + V o M 7 M 8 - V o • Charge injection (CI) and clock-feedthrough (CF) introduce CM jump + and V o - in V o • Dynamic latches are more susceptible to CI and CF errors Vishal Saxena -10-

Dynamic Offset of a Latch Reg. Speed – Linear Model Dynamic offset derives from: Φ • Imbalanced CI and CF • Imbalanced load capacitance • Mismatch b/t M 7 and M 8 • Mismatch b/t M 5 and M 6 + V o • Clock routing - V o  0.5V CM jump   50mV offset  10% imbalance Dynamic offset is usually the dominant offset error in latches Vishal Saxena -11-

Typical CMOS Comparator Reg. Speed – Linear Model V DD • Input-referred latch offset gets divided by M 3 M 4 M 5 M 6 the gain of PA Φ V os • + - Preamp introduces V o V o M 1 M 2 its own offset (mostly V i M 9 static due to V th , W, M 7 M 8 and L mismatches) • PA also reduces V SS kickback noise Preamp Latch Kickback noise disturbs reference voltages, must settle before next sample Vishal Saxena -12-

Comparator Offset Reg. Speed – Linear Model V DD Differential pair mismatch: M 3 M 4 M 5 M 6 2   W Δ   Φ 1 V os   2 L + -   2 ΔV V 2 V o V o   V M 1 M 2 os th ov W 4   V i M 9   L M 7 M 8 g g R   m1 m5 9 A A  V1 V2 g 2 g R V SS m3 m7 9 Preamp Latch  2 2 2 2 V V V V Total input-referred     2 2 os, dyn os,34 os,56 os,78 V V comparator offset: os os,12 2 2 2 2 2 A A A A A V1 V1 V2 V1 V2 Vishal Saxena -13-

Recall: Matching Properties Reg. Speed – Linear Model Suppose parameter P of two rectangular devices has a mismatch error of Δ P. The variance of parameter Δ P b/t the two devices is 2 A   1 st term dominates   2 σ ΔP 2 2 P S D , P for small devices WL where, W and L are the effective width and length, D is the distance 2 A   Threshold: σ 2 2 2 Vth V = +S D th Vth WL    σ β 2 2 A β  2 2 Current factor : S D β β 2 WL Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits , vol. 24, pp. 1433-1439, issue 5, 1989. Vishal Saxena -14-

Recall: Device Sizing for Mismatch Reg. Speed – Linear Model R 1 R 2 … W X X X X X X X X L 10 identical resistors   L L      with std σ 10R with std σ , R R R R 10   1 S R1 2 S 1 R2   W W 10      σ σ 10 σ σ 10 σ 2 2 2 R2 R R1 R2 R1 j  j 1   σ 10 σ σ σ “Spatial 1 1 1      R2 R1  R1  R averaging” R 10R  R  R 10 A WL 2 1 1 Vishal Saxena -15-

Pre-amp Design A fully-differential gain-stage   Avoid or use simple CMFB  Pre-amp gain reduces input referred offset due to the latch  Autozeroing techniques for offset storage and reduction Pre-amp open-loop gain vs tracking bandwidth trade-off   Multiple stages of pre-amp limit bandwidth • Optimum value of stages 2-4 N stages: N   N   A A       ω  0  0 A     N j ω / ω    1   2 ω / ω 1   0 0 1 N A       ω ω ω ω 0 A , 2 N 1   N 3dB 3dB 0 2 Vishal Saxena -16-

Pre-amp (PA) Autozeroing Φ 2 ' M 3 M 4 + - Φ 1 V o V o C V os Φ 2 ' V i V o M 5 M 6 Φ 2 A + - V i V i M 1 M 2  Finite preamp gain: V   OS pre amp , V OS in , A  For the overall comparator :   2 2 V    V 2 OS pre , OS latch , V 2 2 OS in , A A pre pre Vishal Saxena -17-

Pre-amp Design: Pull-up load   NMOS diode pull up :   W L g     m1 1 A Pull-up   L V g W L mL + - V o V o   PMOS diode pull up :   + - V i V i M 1 M 2 μ W L g     m1 n 1 A   L V μ g W L mL p   Resistor pull up :    A g R V m1 L NMOS pull-up suffers from body effect, affecting gain accuracy • PMOS pull-up is free from body effect, but subject to P/N mismatch • Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, • etc.) don’t track transistors; but it is fast! Vishal Saxena -18-

Pre-amp Design: More Gain I p I p M 3 M 4 + - V o V o     μ W L g I 2       m1 n 1 A   3    V μ g I 2 I W L   m3 p p + - V i V i M 1 M 2 I • I p diverts current away from PMOS diodes (M 3 & M 4 ), reducing (W/L) 3 • Higher gain without CMFB • Needs biasing for I p • M 3 & M 4 may cut off for large V in , resulting in a slow recovery Vishal Saxena -19-

Faster Settling Pre-amp M 3 M 5 M 6 M 4 1 -1 r o3 r o5 g m3 g m5 + - V o V o V id g m1 V id r o1 V od + - V i V i M 1 M 2     1 1 g r   dm        m1 o1 DM gain : A g // //r //r //r   V m1 o1 o3 o5 g  g  3   M 7 m3 m5 • NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch • High DM gain, low CM gain, good CMRR • Simple, no CMFB required • (W/L) 34 > (W/L) 56 needs to be ensured for stability Ref: K. Bult and A. Buchwald, “An embedded 240 -mW 10-b 50-MS/s CMOS ADC in 1-mm 2 ,” • JSSC , vol. 32, pp. 1887-1895, issue 12, 1997. Vishal Saxena -20-