Beyond-CMOS Technology Roadmap An Chen Emerging Research Devices - PowerPoint PPT Presentation

Beyond-CMOS Technology Roadmap An Chen Emerging Research Devices (ERD), ITRS

2 For slides, questions, and comments, please contact me at: an.chen@globalfoundries.com

3 Outline • Introduction • Emerging logic devices – CMOS extension vs . beyond-CMOS devices – Beyond-CMOS device assessment • Emerging memory devices – Emerging memory taxonomy and assessment – Promising emerging memories: STTRAM, RRAM, FeFET • Emerging architectures – Beyond von-Neumann architectures – Non-volatility information processing • From scaling driver to function/application driver – More-than-Moore: functional diversification • Summary

4 Technology Innovations Driven by Scaling Beyond-CMOS technologies J. Y.C. Sun, VLSI Tech., T2 (2013)

5 A Roadmap from ITRS PIDS ? Courtesy of: Yuzo Fukuzaki, cited from M. Badaroglu, “More Moore scaling: opportunities and inflection points ,” ERD Meeting: Bridging Research Gap between Emerging Architectures and Devices, Feb 27, 2015

6 “Energy Crisis” on Chip • Scaling  increasing power density • Low-power design and multi-core introduced • Beyond-CMOS devices for low-power solution? Processor peak power density Suppliers: AMD, 60 Intel, SPARC Power density (W/cm 2 ) Symbol size = # of cores 40 20 0 1970 1980 1990 2000 2010 2020 Beyond-CMOS? Year Courtesy of Jonas Wei-ting Chan, Andrew Kahng (UCSD) Source: Bernard S. Meyerson (IBM)

7 ITRS Emerging Research Devices (ERD) Emerging Research Devices Emerging Emerging More-than- New directions devices architectures Moore • Embedded NVMs Sensor Emerging Memory • Storage class memory applications devices for RF Logic • Low power Security Devices with applications learning capabilities ….. A. Chen, J. Hutchby, V. Zhirnov, G. Bourianoff (Ed’s) “Emerging Nanoelectronic Devices” (Wiley , Jan. 2015) http://www.wiley.com/WileyCDA/WileyTitle/productCd- 1118447743,subjectCd-EE13.html

8 ERD Methodology • Selection – Criteria to select technology entries to be added or removed in the ERD chapter – Transition of technology entries in and out of the chapter • Categorization – Categorize technology entries based on the types and mechanisms – Important considerations for materials, e.g., Si, III-V, carbon-based, 2D materials, etc. • Evaluation – Conduct survey-based critical review among ERD experts – Reference to quantitative benchmark from research community

9 Outline • Introduction • Emerging logic devices – CMOS extension vs . beyond-CMOS devices – Beyond-CMOS device assessment • Emerging memory devices – Emerging memory taxonomy and assessment – Promising emerging memories: STTRAM, RRAM, FeFET • Emerging architectures – Beyond von-Neumann architecturess – Non-volatility information processing • From scaling driver to function/application driver – More-than-Moore: functional diversification • Summary

10 Emerging Logic Devices • ITRS ERD categorizes emerging logic devices into three groups based on state variables and mechanisms Non-charge, beyond-CMOS State variable Charge Non-charge Spin wave Nanomagnet DW logic BiSFET ExFET Spin-torque All spin logic SpinFET Atomic sw. RTD Si FET FinFET TFET SET NEMS QCA Ge & III-V NW FET Graphene FET CNT FET Mott FET Neg-C g IMOS Conventional Novel Mechanism CMOS extension Charge, beyond-CMOS

11 CMOS Extension and Beyond-CMOS CMOS extension: K. Kuhn, IEDM, A basic electronic 171 (2012) • New materials switch model  Strain, SiGe, Ge, III- V, CNT, … • New structures a E b  FinFET, gate-all- around, … Beyond-CMOS devices: new mechanism • New transport mechanisms E.g., tunneling • New gating mechanisms E.g., mechanical ferroelectric • New state variables Gate Source Drain E.g., spin

12 Emerging Logic Device Survey Only showing devices with more than 10% vote 20% Percentage of vote  Most promising  Most need of resources 15% 10%

13 Carbon Nanotube (CNT) FET S.J. Han, ERD Emerging logic device assessment workshop. 2014 Advantages: • Scalability • Ultra-thin body • Ballistic transport • Gate-all-around Challenges: • Purity, placement, density • Variability • Contact resistance • NFET for CMOS Rc 9nm L ch FET Size-exclusion chromatography

14 Tunnel Field-Effect-Transistor (TFET) Challenges: QM band-to-band tunneling • Improve I on while keeping SS and I off low enables steep sub-threshold • More stringent material, device, and fabrication slope for low-power operation requirements • Reduce interface state density • Body thickness scaling at advanced nodes • Device variation (body thickness, G-S overlap) TFET surpasses MOSFET in energy at low V dd S. Datta, ERD Emerging logic device assessment workshop. 2014

15 Outline • Introduction • Emerging logic devices – CMOS extension vs . beyond-CMOS devices – Beyond-CMOS device assessment • Emerging memory devices – Emerging memory taxonomy and assessment – Promising emerging memories: STTRAM, RRAM, FeFET • Emerging architectures – Beyond von-Neumann architectures – Non-volatility information processing • From scaling driver to function/application driver – More-than-Moore: functional diversification • Summary

16 Emerging Memory Devices Memory Volatile Nonvolatile ERD SRAM Baseline Prototypical Emerging Ferroelectric Memory FeRAM Flash DRAM FeFET NOR PCM Stand-alone FTJ NAND MRAM Embedded ReRAM STT-RAM PIDS Electrochemical Metallization Bridge Metal Oxide - Bipolar Filamentary Metal Oxide - Unipolar Filamentary 4F 2 footprint Two terminal Metal Oxide - Bipolar Nonfilamentary structures Mott Memory Carbon Memory Macromolecular Memory Molecular Memory

17 Emerging Memory Device Survey Only showing devices with more than 10% vote Percentage of vote 40%  Most promising  Most need of resources 30% 20% 10% 2nd 1st 2nd 1st

18 STTRAM: Spin-Transfer-Torque RAM Challenges: Nonvolatile memory with • Perpendicular-MTJ with sufficient parameters endurance and speed • Integration and manufacturability comparable to those of • Variability control DRAM and SRAM • Cost and commercial factors J. M. Slaughter, IEDM, 29.3 (2012) C. Yoshida, VLSI Tech., 59 (2012)

19 RRAM: Resistive RAM (Including CBRAM) Advantages: Challenges: • Potentially low-cost • Stochastic mechanisms • Potentially high-density • Intrinsic variability • Reasonable speed and endurance • Controllability and repeatability • Versatile devices, materials and structures • Failure mechanisms • Forming requirements (difficulties in down-selection and focus?) G. Jurczak, ERD Emerging logic device 16Gb CBRAM (Micron/Sony) assessment workshop. 2014 Rich Fackenthal, ISSCC (2014)

20 Emerging NVMs toward Commercialization Active industry R&D Testchip reports Early production 8Mb RRAM, 2012 64kB RRAM in 8-bit microcontroller (2013) 32Gb RRAM, 2013 16Gb CBRAM, 2014 RRAM 32Mb, in-plane, 2009 64Mb DDR3 STTRAM (2013) 64Mb, in-plane, 2010 64Mb, p-MTJ, 2010 STTRAM

21 Ferroelectric-FET (FeFET) RAM OFF: I D ~ 0 ON: I D > 0 A key breakthrough: Ferroelectric HfO x J. Muller, ERD Emerging logic device assessment workshop. 2014 Fe-HfOx closes FeFET gate length scaling gap 2 10 physical gate length (  m) 1 10 0 perovskite 10 organic FE-HfO 2 -1 10 -2 10 1995 2000 2005 2010 2015 publication year

22 Outline • Introduction • Emerging logic devices – CMOS extension vs . beyond-CMOS devices – Beyond-CMOS device assessment • Emerging memory devices – Emerging memory taxonomy and assessment – Promising emerging memories: STTRAM, RRAM, FeFET • Emerging architectures – Beyond von-Neumann architectures – Non-volatility information processing • From scaling driver to function/application driver – More-than-Moore: functional diversification • Summary

23 Emerging Architectures • Conventional von Neumann architecture: dominant in today’s computing systems • Novel architectures beyond von Neumann – Cellular automata – Co-located memory-logic (e.g., processor-in-memory, Memory-in-logic, computational memory, nonvolatile logic) – Reconfigurable computing – Cognitive computing (e.g., neuromorphics, machine learning) – Statistical and stochastic computing (e.g., statistical inference, approximate computing) – Collective-effect computing (e.g., coupled oscillator network) – …

24 Brain-Inspired Architectures P.A. Merolla, et al, Science 345 , 668 (2014)

25 Emerging Logic Device Benchmark D.E. Nikonov, IEDM, p. 576 (2012) Spin-torque oscillator logic Graphene P-N Spin-transfer-torque junction domain-wall Alll-spin-logic device Nano-Magnet Logic Hetero-junction tunnel FET Spin-torque majority gate Graphene nano- ribbon tunnel FET Spin-wave device • Benchmark emerging devices at logic gate levels (e.g., 32bit adder) • Energy-delay tradeoffs extend to beyond-CMOS devices

26 Unique Properties of Beyond-CMOS Devices • Nonvolatility – Built-in memory in logic devices • Efficient logic implementation – E.g., majority gate • Structural / layout regularity – E.g., Quantum Cellular Automata (QCA), crossbar arrays • Self-adaptive property • Coherent or collective behaviors – Low-power switching, robustness Novel architectures and designs enabled by these unique device characteristics?