14 Gb/s AC Coupled Receiver in 90 nm CMOS Masum Hossain & Tony - PowerPoint PPT Presentation

14 Gb/s AC Coupled Receiver in 90 nm CMOS Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca

OUTLINE • Chip-to-Chip link overview • AC interconnects • Link modelling • ISI & sensitivity • AC Receiver architecture • Implementation in 0.18 um CMOS • Measured results • Speed and sensitivity improvement techniques • Implementation in 90nm CMOS • Measured results • Conclusion 2

Chip-to-Chip Link Overview chip-to-chip link chip-to-chip link DC coupled serial link DC coupled serial link AC coupled serial link AC coupled serial link AC coupled link over AC coupled link over Proximity coupling Proximity coupling PCB trace [Luo‘05] PCB trace [Luo‘05] [Miura ‘05, Drost ‘04] [Miura ‘05, Drost ‘04] • Achieve high speed Goals : • Small area : small coupling capacitor • High sensitivity • Achieve good FOM mW/Gb/s 3

AC Coupled Link Overview Input Pulse swing (mV pp ) Input Pulse swing (mV pp ) 500 500 Kohn ISCAS’95 Kohn ISCAS’95 Kohn ISCAS’95 400 400 Gabara JSSC’97 Gabara JSSC’97 Gabara JSSC’97 300 300 Kim CICC’04 Kim CICC’04 200 200 Drost JSSC’04 Drost JSSC’04 Drost JSSC’04 Luo JSSC’06 Luo JSSC’06 Luo JSSC’06 Luo CICC’06 Luo CICC’06 Luo CICC’06 100 100 Miura ISSCC’07 Miura ISSCC’07 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 Data Rate (Gb/s) Data Rate (Gb/s) � Achieves high density Low speed � 3-D Integration is possible Complexity increases � All NMOS I/O driver Have poor FOM mW/Gb/s 1. Multi-standard integration >10 mW/Gb/s 2. Compatible common mode 3. DC offset immune 4

AC Coupled Link Overview Input Pulse swing (mV pp ) Input Pulse swing (mV pp ) 500 500 Kohn ISCAS’95 Kohn ISCAS’95 Kohn ISCAS’95 400 400 Gabara JSSC’97 Gabara JSSC’97 Gabara JSSC’97 Increase 300 300 speed Kim CICC’04 Kim CICC’04 200 200 Drost JSSC’04 Drost JSSC’04 Drost JSSC’04 Luo JSSC’06 Luo JSSC’06 Luo JSSC’06 Luo CICC’06 Luo CICC’06 Luo CICC’06 0.18 um 0.18 um 100 100 0.18 um 0.18 um 90 nm 90 nm Miura ISSCC’07 Miura ISSCC’07 Increase 90 nm 90 nm sensitivity 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 Data Rate (Gb/s) Data Rate (Gb/s) Our goal is to increase both sensitivity and speed using standard CMOS process 5

AC Coupled Link Modeling W/o T line W/o T line With 30 cm With 30 cm 20 dB/dec 20 dB/dec T line T line 6

ISI & Rx Sensitivity 14 Gb/s input eye 40 mV 40 mV 20 mV 20 mV 80 mV 80 mV C = 80 fF C = 150 fF C = 50 fF Coupling capacitor area ISI sensitivity requirement Coupling capacitor area ISI sensitivity requirement 7

Rx Architecture AC coupled Rx Non-linear Rx Linear Rx • 8b10b code • Inductors Data recovery Clock forwarded • Not robust without clock [Miura’05] [Drost’04,Luo’05] • Complexity & power • Timing margin • Robust • Clock distribution • Low power • Requires high speed hysteresis 8

Non-linear Clock less Rx Hysteresis – Regenerates data from the transitions 9

Hysteresis Architecture Positive feedback Positive feedback • Hysteresis Condition : g m R L > 1 • Unstable points : M,N (large gain g m R L ) • Bi-Stable points : A,B (non-linear gain) 10

Hysteresis Analysis R L Latch Mode Δ V in << V th g m g m-in [A-B] I tail ( ) ( ) = + − v t I R v t g R − out tail L in m in L ( ) ( ) << ≈ + V t V v t V in th out 0 ( ) ( ) ≈ ≈ V t V v t 0 in th out 2g m => = sensitivity 2 V V th o g − m in 11

Hysteresis Analysis R L C Tot Switching Mode Δ V in ≈ V th g m g m-in [B-C] t exp ⎛ ⎞ ( ) ( ) = − − v t V Kv t ⎜ ⎟ 0 0 in τ ⎝ ⎠ settle exponential Linear g R R C − = τ = m in L L Tot K − − settle g R 1 g R 1 m L m L 12

Hysteresis Analysis R L Latch Mode Δ V in >> V th g m g m-in [C-D] I tail ( ) ( ) = − − v t I R v t g R − out tail L in m in L ( ) ( ) >> ≈ − v t V v t V in th out 0 13

Hysteresis Architecture R L C Tot g m g m-in R C τ = L Tot − settle g R 1 m L 14

Hysteresis Design Consideration R L R L C Tot C Tot g m g m g m-in g m-in R C τ = L Tot • Speed Improvement − settle g R 1 m L • Increase C Tot • Increase g m R L • Increase power consumption • Reduce C Tot 15

Improved Hysteresis Architecture • Condition for hysteresis : (g m2 R L2 )(g m3 R L1 ) >1 • g m2 buffers node V HYST from capacitive loading • R L2 , R L3 distributes the output capacitance 16

10+ Gb/s Hysteresis Design R out R out g m-in =6.5 mS R L R L g m2 =7.1 mS g m3 g m3 g m3 =7.8 mS R L =300-ohm g m-in g m-in g m2 g m2 R out =80-ohm ( )( ) = > Hysteresis condition : • g R g R 1 3347 1 m2 L m3 OUT . 2g − Sensitivity & Logic levels : = = = m in • V 40mV; 2 V V 76mV th 0 th g m2 τ = = Rise time: R C 18ps • HYST L Tot Power Consumption: (1.8 X10) < 20 mW • 17

Implementation & Measurement 150 fF 600 um Capacitance Scope 400 um Off chip termination On chip channel • Active area 200 um X 300 um • Only single ended testing was possible • Measured swing will be 25% of actual swing 18

19 10 Gb/s Measured eye 20 mV

10 Gb/s Measured sequence Error free operation verified with 127 bit pattern 20

14 Gb/s Measured eye Rx eye Recovered eye 20 mV 50 mV 21

Performance Summary • Process 0.18 um CMOS • Bit rate 10+ Gb/s • Output Eye amplitude 80 mVp-p differential • Coupling capacitor of 150 fF • Power consumption 20 mW 90-nm Implementation • Coupling C = 80fF : improve sensitivity • Eye Amplitude > 250 mV : increase output swing • Bit Rate = 15 Gb/s : improve speed 22

Improving sensitivity 5x Improvement in sensitivity !! 23

Bandwidth of the Pre-amp +V th +V th Slope eye [10 Gb/s] -V th -V th Jitter due to pre-amp (BW = 8GHz) Recovered NRZ eye [10 Gb/s] Pre-amp requires more BW in AC coupled receivers !!! 24

Bandwidth of the Pre-amp BW 8 GHz Rise Time Gain 18 dB 25 ps 16 Gb/s eye diagram 14 Gb/s eye diagram How can we improve Jitter and ISI ?? 25

Speed Improvement • Improve speed by using available data transitions • How to match the latency ? • Can we have sufficient BW ? 26

Speed Improvement ω 2 A = vo n A v + ζω + ω 2 2 s 2 s n n [Galal ’02] 27

Speed Improvement 16 Gb/s eye diagram 16 Gb/s eye diagram V HYST V EQ 28

Implementation in 90-nm CMOS • Each stage A V =g m R L = 1.9 • Bandwidth >15 GHz • Power consumption 2mW • Total Gain: 7.6 > 5 • Bandwidth = 11 GHz • Total power = 8 mW 29

Implementation in 90-nm CMOS Pre-amp Pre-amp + Slope-amp 2 GHz 30

Implementation in 90-nm CMOS 10 Gb/s eye V HYST V HYST 200 mV 200 mV 200 mV 200 mV -200 mV -200 mV -200 mV -200 mV V SLOPE V SLOPE 200 mV 200 mV 200 mV -200 mV -200 mV -200 mV 0 0 100pS 100pS 200pS 200pS 300pS 300pS 400pS 400pS 31

Implementation in 90-nm CMOS Arrow indicates error bits Transmitted sequence Bit period 50 ps 32

Implementation in 90-nm CMOS 300 um Slope Amp 150 um 80 fF Pre-amp Adder Hysteresis • Active area 100 um X 300 m • Total power 32 mW 33

10 Gb/s Measured eye 50 mV Slope path was turned off at 10 Gb/s 34

14 Gb/s Measured eye Slope Path OFF Slope Path ON Vertical scale : 25 mV/div Vertical scale : 50 mV/div Horizontal scale : 50 ps/div Horizontal scale : 50 ps/div 35

14 Gb/s Measured BER Bathtub 14 Gb/s recovered eye with 14 Gb/s recovered eye with Hysteresis only Hysteresis + Slope-path 36

Conclusion • 10+ Gb/s hysteresis circuit topology is implemented and tested in 0.18-um CMOS process (FOM 2 mW/Gb/s) • High speed AC coupled receiver architecture is introduced: 1. Additional slope path reduces ISI at hysteresis output 2. Additional slope path reduces jitter • 14 Gb/s AC coupled receiver is implemented and tested in 90-nm CMOS • FOM 1.80 mW/Gb/s @ 10 Gb/s • FOM 2.28 mW/Gb/s @ 14 Gb/s 37