Y86-64 Instruction Set Byte 0 1 2 3 4 5 6 7 8 9 halt 0 - PDF document

Y86-64 Instruction Set Byte 0 1 2 3 4 5 6 7 8 9 halt 0 0 Computer Architecture: nop 1 0 Y86-64 Sequential Implementation cmovXX rA , rB 2 fn rA rB 3 0 F irmovq V , rB rB V rmmovq rA , D ( rB ) 4 0 rA rB D CSci 2021: Machine Architecture and Organization March 23rd-25th, 2020 mrmovq D ( rB ), rA 5 0 rA rB D Your instructor: Stephen McCamant OPq rA , rB 6 fn rA rB jXX Dest 7 Dest fn Based on slides originally by: call Dest 8 0 Dest Randy Bryant and Dave O’Hallaron ret 9 0 pushq rA A 0 F rA popq rA B 0 F rA – 1 – – 2 – CS:APP3e CS:APP3e Building Blocks Hardware Control Language fun Combinational Logic  Very simple hardware description language A = A  Can only express limited aspects of hardware operation  Compute Boolean functions of L  Parts we want to explore and modify inputs U B 0  Continuously respond to input Data Types MUX changes  bool : Boolean 1  Operate on data and implement  a , b , c , … control  int : words  A , B , C , …  Does not specify word size---bytes, 32- bit words, … Storage Elements valA A Statements srcA  Store bits valW Register W dstW  bool a = bool-expr ; file  Addressable memories valB B  int A = int-expr ;  Non-addressable registers srcB Clock  Loaded only as clock rises Clock – 6 – – 7 – CS:APP3e CS:APP3e SEQ Hardware newPC PC HCL Operations valE, valM Structure Write back valM State  Classify by type of value returned Data Data Memory memory memory  Program counter register (PC) Boolean Expressions Addr, Data  Condition code register (CC)  Logic Operations  Register File valE  a && b , a || b , !a  Memories CC CC  Word Comparisons ALU  Access same memory space Execute Cnd ALU aluA, aluB  A == B , A != B , A < B , A <= B , A >= B , A > B  Data: for reading/writing program data  Set Membership  Instruction: for reading valA, valB  A in { B, C, D } instructions » Same as A == B || A == C || A == D srcA , srcB Decode dstA, dstB A A B B Register Register M M Instruction Flow Register Register file file file file E E Word Expressions  Read instruction at address icode , ifun valP rA , rB specified by PC valC  Case expressions Instruction Instruction PC PC  [ a : A; b : B; c : C ]  Process through stages Fetch memory memory increment increment  Evaluate test expressions a , b , c , … in sequence  Update program counter  Return word expression A , B , C , … for first successful test PC – 8 – CS:APP3e – 9 – CS:APP3e

newPC PC SEQ Stages Instruction Decoding valE, valM Write back valM Optional Fetch Optional Data Data Memory memory memory  Read instruction from instruction memory Addr, Data 5 0 rA rB D Decode valE  Read program registers CC CC icode ALU ALU Execute Cnd Execute aluA, aluB ifun  Compute value or address rA rB valA, valB Memory valC  Read or write data srcA, srcB Decode dstA, dstB A A B B Register Register Register Register M M file file file file Instruction Format E E Write Back icode ifun valP , rA , rB  Write program registers  Instruction byte icode:ifun valC Instruction PC Instruction PC  Optional register byte rA:rB PC memory increment Fetch memory increment  Optional constant word valC  Update program counter PC – 10 – – 11 – CS:APP3e CS:APP3e Executing Arith./Logical Operation Stage Computation: Arith/Log. Ops OPq rA, rB OPq rA , rB 6 fn rA rB icode:ifun  M 1 [PC] Read instruction byte rA:rB  M 1 [PC+1] Read register byte Fetch Fetch Memory valP  PC+2  Read 2 bytes  Do nothing Compute next PC valA  R[rA] Read operand A Decode Write back Decode valB  R[rB] Read operand B  Read operand registers  Update register valE  valB OP valA Perform ALU operation Execute Execute PC Update Set CC Set condition code register Memory  Perform operation  Increment PC by 2 Write R[rB]  valE Write back result  Set condition codes back PC  valP PC update Update PC  Formulate instruction execution as sequence of simple steps  Use same general form for all instructions – 12 – – 13 – CS:APP3e CS:APP3e Executing rmmovq Stage Computation: rmmovq rmmovq rA, D(rB) rmmovq rA , D ( rB) 4 0 rA rB D icode:ifun  M 1 [PC] Read instruction byte rA:rB  M 1 [PC+1] Read register byte Fetch Fetch Memory valC  M 8 [PC+2] Read displacement D valP  PC+10  Read 10 bytes  Write to memory Compute next PC valA  R[rA] Read operand A Decode Write back Decode valB  R[rB] Read operand B  Read operand registers  Do nothing valE  valB + valC Compute effective address Execute Execute PC Update M 8 [valE]  valA Memory Write value to memory  Compute effective address  Increment PC by 10 Write back PC  valP PC update Update PC  Use ALU for address computation – 14 – CS:APP3e – 15 – CS:APP3e

Executing popq Stage Computation: popq popq rA popq rA b 0 rA 8 icode:ifun  M 1 [PC] Read instruction byte rA:rB  M 1 [PC+1] Read register byte Fetch Fetch Memory valP  PC+2 Compute next PC  Read 2 bytes  Read from old stack pointer valA  R[ %rsp ] Read stack pointer Decode Write back Decode valB  R[ %rsp ] Read stack pointer  Read stack pointer  Update stack pointer valE  valB + 8 Increment stack pointer Execute  Write result to register Execute valM  M 8 [valA] Memory Read from stack PC Update  Increment stack pointer by 8 R[ %rsp ]  valE Write Update stack pointer  Increment PC by 2 R[rA]  valM Write back result back PC  valP PC update Update PC  Use ALU to increment stack pointer  Must update two registers  Popped value  New stack pointer – 16 – – 17 – CS:APP3e CS:APP3e Executing Conditional Moves Stage Computation: Cond. Move cmovXX rA, rB cmovXX rA , rB 2 fn rA rB icode:ifun  M 1 [PC] Read instruction byte rA:rB  M 1 [PC+1] Read register byte Fetch Fetch Memory valP  PC+2  Read 2 bytes  Do nothing Compute next PC valA  R[rA] Read operand A Decode Write back Decode valB  0  Read operand registers  Update register (or not) valE  valB + valA Pass valA through ALU Execute If ! Cond(CC,ifun) rB  0xF Execute PC Update (Disable register update) Memory  If !cnd, then set destination  Increment PC by 2 Write R[rB]  valE Write back result register to 0xF back PC  valP PC update Update PC  Read register rA and pass through ALU  Cancel move by setting destination register to 0xF  If condition codes & move condition indicate no move – 18 – – 19 – CS:APP3e CS:APP3e Executing Jumps Stage Computation: Jumps jXX Dest jXX Dest 7 fn Dest icode:ifun  M 1 [PC] Read instruction byte Not taken XX XX fall thru: Fetch valC  M 8 [PC+1] Read destination address valP  PC+9 Fall through address XX XX Taken target: Decode Fetch Memory Execute Cnd  Cond(CC,ifun)  Read 9 bytes  Do nothing Take branch? Memory  Increment PC by 9 Write back Write Decode  Do nothing back  Do nothing PC  Cnd ? valC : valP PC Update PC update Update PC Execute  Set PC to Dest if branch taken or to incremented PC  Compute both addresses  Determine whether to take if not branch branch based on jump  Choose based on setting of condition codes and branch condition and condition condition codes – 20 – CS:APP3e – 21 – CS:APP3e