EE 109 Unit 8 MIPS Instruction Set Architecting a vocabulary for - PowerPoint PPT Presentation

8.1 8.2 EE 109 Unit 8 – MIPS Instruction Set Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 8.3 8.4 Instruction Set Architecture (ISA) Components of an ISA 1. ________ and Address Size • Defines the _________________ of the processor – 8-, 16-, 32-, 64-bit and memory system 2. Which instructions does the processor support • Instruction set is the ____________ the HW can – SUBtract instruc. vs. NEGate + ADD instrucs. understand and the SW is composed with 3. ________________________ of instructions • 2 approaches – How is the operation and operands represented with 1’s and 0’s – _____ = ___________ instruction set computer 4. __________ accessible to the instructions • Large, rich vocabulary – Faster than accessing data from memory • More work per instruction but slower HW 5. Addressing Modes – _____ = ___________ instruction set computer – How instructions can specify location of data operands • Small, basic, but sufficient vocabulary • Less work per instruction but faster HW

8.5 8.6 General Instruction Format Issues Historic Progression of Data Size & Registers Processor Year Trans. Data Size GPRs • Instructions must specify three things: Count – ______________________________________ 8088 1979 29K 8 8 – Source operands 80286 1982 134K 16 8 • Usually 2 source operands (e.g. X+Y) 80386/486 ’85/’89 275K/1.1 32 8 – ______________________________________ 8M Pentium 1993 3.1M 32 >8 • Example: ADD $8, $9, $10 ($8 = $9 + $10 where $ = Register) Pentium 4 2000 42M 32 >= 128 • Binary (machine-code) representation broken into fields of bits for each part Core 2 Duo 2006 291M 64 >= 128 6-core Core i7 2011 2.27B 64 >= 128 OpCode Src. 1 Src. 2 Dest. Shift Amount Function 000000 01001 01010 01000 00000 100000 MIPS 1999 var. 32 32 Arith. $9 $10 $8 Unused Add 8.7 8.8 Historical Instruction Formats Historical Instruction Format Examples • Consider the pros and cons of each format when performing the set of • Different instruction sets specify these differently operations – 3 operand instruction set (MIPS, PPC, ARM) – F = X + Y – Z – G = A + B • Similar to example on previous page • Simple embedded computers often use single operand format • Format: ADD DST, SRC1, SRC2 (DST = SRC1 + SRC2) – Smaller data size (8-bit or 16-bit machines) means limited instruc. size • Modern, high performance processors use 2- and 3-operand formats – 2 operand instructions (Intel / Motorola 68K) • Second operand doubles as source and destination Single-Operand Two-Operand Three-Operand • Format: ADD SRC1, S2/D (S2/D = SRC1 + S2/D) LOAD X MOVE F,X ADD F,X,Y – 1 operand instructions (Old Intel FP, Low-End Embedded) ADD Y ADD F,Y SUB F,F,Z SUB Z SUB F,Z ADD G,A,B STORE F MOVE G,A • Implicit operand to every instruction usually known as the LOAD A ADD G,B ADD B Accumulator (or ACC) register STORE G • Format: ADD SRC1 (ACC = ACC + SRC1) (+) Smaller size to encode each Compromise of two extremes (+) More natural program style instruction (+) Smaller instruction count (-) Higher instruction count to (-) Larger size to encode each load and store ACC value instruction

8.9 8.10 MIPS Instruction Format Which Instructions • _______________ operand format • In this class we'll focus on assembly to do the following Load/Store Architecture – Most ALU instructions use 3 registers as tasks (shown with the corresponding MIPS assembly their operands mnemonics) Proc. Mem. – All operations are performed on entire 32- – Load variables (data) from memory (or I/O) [LW,LH,LB] bits (no size distinction) 1.) Load operands to proc. registers – Example: ADD $t0, $t1, $t2 – Perform arithmetic, logical, and shift instructions in the CPU • ______________ architecture [ADD,SUB,AND,OR,SLL,SRL,SRA] Proc. Mem. – Load (read) data values from memory into a – Store variables (data) back to memory after computation is register complete [SW, SH, SB] 2.) Proc. Performs operation using – Perform operations on registers register values – Compare data [SLT] – Store (write) data values back to memory – "Branch" to other code (to implement if and loops) – Different load/store instructions for [BEQ,BNE,J] Proc. Mem. different operand sizes (i.e. byte, half, word) – Call subroutines/functions [JAL, JR] 3.) Store results back to memory 8.11 8.12 MIPS ISA • _____________ Style • ______________ internal / __________ external data size – Registers and ALU are 32-bits wide – Memory bus is logically 32-bits wide (though may be physically wider) • Registers – ______ General Purpose Registers (GPR’s) • For integer and address values • A few are used for specific tasks/values MIPS INSTRUCTION OVERVIEW – 32 Floating point registers • Fixed size instructions – All instructions encoded as a single ______-bit word – Three operand instruction format (dest, src1, src2) – Load/store architecture (all data operands must be in registers and thus loaded from and stored to memory explicitly)

8.13 8.14 MIPS GPR’s MIPS Programmer-Visible Registers Assembler Name Reg. Number Description • General Purpose Registers GPR’s (GPR’s) $zero $0 Constant 0 value $0 - $31 – Hold data operands or $at $1 Assembler temporary addresses (pointers) to data $v0-$v1 $2-$3 Procedure return values or expression stored in memory evaluation • Special Purpose Registers $a0-$a3 $4-$7 Arguments/parameters – ___: ____________ ___(32-bits) $t0-$t7 $8-$15 Temporaries • Holds the address of the next 32-bits $s0-$s7 $16-$23 Saved Temporaries instruction to be fetched from memory & executed $t8-$t9 $24-$25 Temporaries PC: – HI: Hi-Half Reg. (32-bits) $k0-$k1 $26-$27 Reserved for OS kernel • For MUL, holds 32 MSB’s of Recall multiplying two 32-bit result. For DIV, holds 32-bit numbers yields a 64-bit result $gp $28 Global Pointer (Global and static remainder HI: variables/data) – LO: Lo-Half Reg. (32-bits) $sp $29 Stack Pointer LO: • For MUL, holds 32 LSB’s of $fp $30 Frame Pointer result. For DIV, holds 32-bit MIPS Core quotient $ra $31 Return address for current procedure Special Purpose Registers Avoid using the yellow (highlighted) registers for anything other than its stated use 8.15 8.16 Instruction Format • 32-bit Fixed Size Instructions broken into 3 types (R-, I-, and J-) based on which bits ______________… • ___________ 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits – Arithmetic/Logic __-Type opcode rs (src1) rt (src2) rd (dest) shamt function instructions add $5,$7,$8 000000 00111 01000 00101 00000 100000 – 3 register operands or shift amount 6-bits 5-bits 5-bits 16-bits __-Type • ___________ opcode rs (src1) rt (src/dst) immediate Performing Arithmetic, Logic, and Shift Operations lw $18, -4($3) 100011 00011 10010 1111 1111 1111 1100 – Use for data transfer, IMPORTANT R-TYPE INSTRUCTIONS branches, etc. 6-bits 26-bits – 2 registers + __-Type opcode Jump address 16-bit const. j 0x0400018 000010 0000 0100 0000 0000 0000 0001 10 • _________ Each type uses portions of the instruction to "code" certain aspects of – 26-bit jump address the instruction. But they all start with an opcode that helps determine – We'll cover this later which type will be used.