EE 457 Unit 3 Instruction Sets With Focus on our Case Study: MIPS - PowerPoint PPT Presentation

3.1 3.2 EE 457 Unit 3 Instruction Sets With Focus on our Case Study: MIPS INSTRUCTION SET OVERVIEW 3.3 3.4 Instruction Sets Instruction Set Architecture (ISA) • Defines the software interface of the processor and • 2 approaches memory system – CISC = Complex instruction set computer • Large, rich vocabulary • Instruction set is the vocabulary the HW can • More work per instruction, slower clock cycle understand and the SW is composed with – RISC = Reduced instruction set computer • Most assembly/machine instructions fall into one of • Small, basic, but sufficient vocabulary three categories • Less work per instruction, faster clock cycle – ____________________________ • Usually a simple and small set of instructions with regular format facilitates building faster processors – ____________________________ – ____________________________

3.5 3.6 MIPS ISA MIPS Programmer-Visible Registers GPR’s • • General Purpose Registers (GPR’s) RISC Style MIPS Core – Hold data operands or addresses $0 - $31 • 32-bit internal / 32-bit external data size (pointers) to data stored in memory – Registers and ALU are 32-bits wide • Special Purpose Registers – Memory bus is logically 32-bits wide (though may be physically – PC: ______________(32-bits) wider) • Holds the _________ of the next • Registers ___________ to be fetched from memory & executed 32-bits – 32 General Purpose Registers (GPR’s) – HI: Hi-Half Reg. (32-bits) • For integer and address values • For MUL, holds 32 MSB’s of PC: result. For DIV, holds 32-bit • A few are used for specific tasks/values remainder – 32 Floating point registers – LO: Lo-Half Reg. (32-bits) MEM • Fixed size instructions • For MUL, holds 32 LSB’s of HI: add 0xA140 result. For DIV, holds 32-bit – All instructions encoded as a single 32-bit word quotient ?? sub LO: – Three operand instruction format (dest, src1, src2) – Load/store architecture (all data operands must be in registers and thus loaded from and stored to memory explicitly) Special Purpose Registers 3.7 3.8 MIPS GPR’s MIPS Programmer-Visible Registers Assembler Name Reg. Number Description GPR’s • Coprocessor 0 Registers $zero $0 Constant 0 value – Status Register $0 - $31 $f0 - $f31 $at $1 Assembler temporary • Holds various control bits for processor modes, handling $v0-$v1 $2-$3 Procedure return values or expression interrupts, etc. evaluation – Cause Register $a0-$a3 $4-$7 Arguments/parameters • Holds information about exception (error) conditions $t0-$t7 $8-$15 Temporaries • Coprocessor 1 Registers 32-bits 64 or more – Floating-point registers $s0-$s7 $16-$23 Saved Temporaries Coprocessor 1 – – Can be used for single or PC: Floating-point Regs. $t8-$t9 $24-$25 Temporaries double-precision (i.e. at least 64-bits wides) $k0-$k1 $26-$27 Reserved for OS kernel Status: $gp $28 Global Pointer (Global and static Cause: HI: variables/data) Coprocessor 0 – $sp $29 Stack Pointer LO: Status & Control Regs $fp $30 Frame Pointer MIPS Core $ra $31 Return address for current procedure Special Purpose Registers

3.9 3.10 General Instruction Format Issues Historical Instruction Format Options • Instructions must specify three things: • Different instruction sets specify these differently – 3 operand instruction set (MIPS, PPC) – _____________________________ • Usually all 3 operands in registers – _____________________________ • Format: ADD DST, SRC1, SRC2 (DST = SRC1 + SRC2) – _____________________________ – 2 operand instructions (Intel / Motorola 68K) • Second operand doubles as source and destination • Example: ADD $3, $1, $2 ($3 = $1 + $2) • Format: ADD SRC1, S2/D (S2/D = SRC1 + S2/D) • Binary (machine-code) representation broken into – 1 operand instructions (Low-End Embedded, Java Virtual Machine) fields of bits for each part • Implicit operand to every instruction usually known as the ______________________ register • Format: ADD SRC1 (ACC = ACC + SRC1) OpCode Src. 1 Src. 2 Dest. Shift Amount Function – 0 operand instructions / ___________architecture 000000 00001 00010 00011 00000 100000 • Push operands on a stack: PUSH X, PUSH Y • ALU operation: ADD (Implicitly adds top two items on stack: X + Y Arith. $1 $2 $3 Unused Add & replaces them with the sum) 3.11 3.12 Addressing Modes General Instruction Format Issues • Consider the pros and cons of each format when performing the set of • Addressing modes refers to how an instruction specifies operations _______________ the operands are – F = X + Y – Z – G = A + B – Can be in a ______________, _____________, or in the machine code • Simple embedded computers often use single operand format of the instruction (immediate value) – Smaller data size (8-bit or 16-bit machines) means limited instruc. size • MIPS: All data operands for arithmetic instructions must be in • Modern, high performance processors use 2- and 3-operand formats a register Stack Arch. Single-Operand Two-Operand Three-Operand • But what about something like: $8 = $8 + A[i] LOAD X MOVE F,X ADD F,X,Y – Intel instructions would allow: ADD $8,A[i] ADD F,Y SUB F,F,Z SUB F,Z ADD G,A,B • A[i] is in memory MOVE G,A ADD G,B – MIPS require a ________________ to read data from memory into a register (+) Smaller size to (+) More natural • _________________ encode each program style • ADD $8,$8,$9 instruction (+) Smaller instruction count

3.13 3.14 Operand Addressing Load/Store Addressing • When we load or store from/to memory how do we • Load/Store architecture Load/Store Architecture specify the address to use? Do we need – Load operands from memory into a register sophisticated/exotic address modes (auto-increment, i = 0; – Perform operations on registers and put results base+scaled index?) While(i < MAX) Proc. Mem. back into other registers x = x + A[i++]; • Option 1: Direct Addressing – Store results back to memory – Constant address: LW $8, 0xA140 1.) Load operands to proc. registers – Because ALU instructions only access registers, – Insufficient! the CPU design can be simpler and thus faster MEM – Would have to translate to: • A[0] @ 0xA140 00 Most modern processors follow this approach • LW $8, 0xA140 Proc. Mem. A[1] @ 0xA144 00 • Older designs • ___________________________ A[2] @ 0xA148 00 – Register/Memory Architecture (Intel) 2.) Proc. Performs operation using A[3] @ 0xA14C 00 • ___________________________ • 1 operand of a ALU instruc. can be in a reg. or mem. but register values the other must be in a register – Memory/Memory Architecture (DEC VAX) • Operands of ALU instruc. can be in any combination of Proc. Mem. memory or registers • ADD addrDst, addrSrc1, addrSrc2 3.) Store results back to memory 3.15 3.16 Load/Store Addressing Immediate Addressing • Option 2: ________________________ • Suppose you want to increment a variable (register) – Put address in a register: $9 = 0xA140 – $8 = $8 + 1 – LW uses variable address in reg.: LW $8,__________ i = 0; – Increment address via normal ADD instruc. (ADD $9,$9, _____) – Where do we get the 1 from? While(i < MAX) x = x + A[i++]; – Sufficient! • Could have compiler/loader ______________________ • Option 3: ______________________________ __________________ and then load it from memory – Sums a constant offset with variable address in register MEM • Constant usage is very common, so instruction sets usually – Put address in a register: $9 = 0xA140 A[0] @ 0xA140 00 – LW uses variable address in reg.: LW $8, 0 ($9) [___________] support a constant to be directly placed ______ A[1] @ 0xA144 00 – LW uses variable address in reg.: LW $8, 4 ($9) [___________] ____________________ A[2] @ 0xA148 00 – Sufficient! • Known as immediate value because it is immediately available A[3] @ 0xA14C 00 with the instruction machine code itself • Example: ADDI $8,$8,1