What Is ISA? What Is ISA? Instruction set architecture is the structure Instruction set architecture is the structure Lecture 3: Instruction Lecture 3: Instruction of a computer that a machine language of a computer that a machine language programmer (or a compiler) must programmer (or a compiler) must Set Architecture Set Architecture understand to write a correct (timing understand to write a correct (timing independent) program for that machine. independent) program for that machine. For IBM System/360, 1964 For IBM System/360, 1964 ISA types, register usage, ISA types, register usage, memory addressing, memory addressing, endian endian � Class ISA types: Stack, Accumulator, and Class ISA types: Stack, Accumulator, and � and alignment, quantitative and alignment, quantitative General- General -purpose register purpose register evaluation evaluation � ISA is mature and stable ISA is mature and stable � – – Why do we study it? Why do we study it? 1 1 2 2 Stack Stack Accumulator Accumulator � The accumulator provides an The accumulator provides an Implicit operands on stack � implicit input, and is the implicit input, and is the Ex. C = A + B implicit place to store the implicit place to store the Push A result. result. Push B � Ex. C = A + B Ex. C = A + B � Add Load R1, A Load R1, A Pop C Add R3, R1, B Add R3, R1, B Good code density; used in Store R3, c Store R3, c 60’s-70’s; now in Java VM � Used before 1980 Used before 1980 � 3 3 4 4 General General- -purpose Registers purpose Registers Variants of GRP Architecture Variants of GRP Architecture � General General- -purpose registers are preferred by purpose registers are preferred by � Number of operands in ALU instructions: two or Number of operands in ALU instructions: two or � � compilers compilers three three – Reduce memory traffic Reduce memory traffic – Add R1, R2, R3 Add R1, R2, R3 Add R1, R2 Add R1, R2 – – Improve program speed Improve program speed � Maximal number of memory operands in ALU Maximal number of memory operands in ALU � – Improve code density – Improve code density instructions: zero, one, two, or three instructions: zero, one, two, or three � Usage of general Usage of general- -purpose registers purpose registers � Load R1, A Load R1, A Load R1, A Load R1, A – Holding temporal variables in expression evaluation Holding temporal variables in expression evaluation – Load R2, B Load R2, B Add R3, R1, B Add R3, R1, B – – Passing parameters Passing parameters Add R3, R1, R2 Add R3, R1, R2 – Holding variables – Holding variables � GPR and RISC and CISC GPR and RISC and CISC � Three popular combinations Three popular combinations � � – – RISC ISA is extensively used for desktop, server, and RISC ISA is extensively used for desktop, server, and – register – register- -register (load register (load- -store): 0 memory, 3 operands store): 0 memory, 3 operands embedded: MIPS, PowerPC, UltraSPARC embedded: MIPS, PowerPC, UltraSPARC, ARM, MIPS16, , ARM, MIPS16, – register – register- -memory: 1 memory, 2 operands memory: 1 memory, 2 operands Thumb Thumb – – memory memory- -memory: 2 memories, 2 operands; or 3 memory: 2 memories, 2 operands; or 3 – CISC: IBM 360/370, VAX, and Intel 80x86 – CISC: IBM 360/370, VAX, and Intel 80x86 memories, 3 operands memories, 3 operands 5 5 6 6 1
Register- Register -memory memory Register- Register -register (Load register (Load- -store) store) � There is no implicit There is no implicit � Both operands are registers Both operands are registers � � operand operand � Values in memory must be Values in memory must be � � One input operand is One input operand is loaded into a register and loaded into a register and � register, and one in register, and one in stored back stored back memory memory � Ex. C = A + B Ex. C = A + B � Ex. C = A + B Ex. C = A + B Load R1, A Load R1, A Load R1, A Load R1, A Load R2, B Load R2, B Add R3, R1, B Add R3, R1, B Add R3, R1, R2 Add R3, R1, R2 Store R3, C Store R3, C Store R3, C Store R3, C � Processors include VAX, Processors include VAX, � Processors: MIPS, SPARC Processors: MIPS, SPARC � � 80x86 80x86 7 7 8 8 How Many Registers? How Many Registers? ISA and Performance ISA and Performance CPU time = #inst × CPI × cycle time If the number of registers increase: If the number of registers increase: CPU time = #inst × CPI × cycle time � RISC with Register RISC with Register- -Register instructions Register instructions � � Allocate more variables in registers (fast Allocate more variables in registers (fast � � Simple, fix Simple, fix- -length instruction encoding length instruction encoding � accesses) accesses) � Simple code generation Simple code generation � � Regularity in CPI Regularity in CPI � � Reducing code spill Reducing code spill � � Higher instruction counts Higher instruction counts � � Reducing memory traffic Reducing memory traffic � Lower instruction density Lower instruction density � � � CISC with Register CISC with Register- -memory instructions memory instructions � � Longer register Longer register specifiers specifiers (difficult encoding) (difficult encoding) � � No extra load in accessing data in memory No extra load in accessing data in memory � � Increasing register access time (physical Increasing register access time (physical � Easy encoding Easy encoding � � � Operands being not equivalent Operands being not equivalent registers) registers) � � Restricted #registers due to encoding memory address Restricted #registers due to encoding memory address � � More registers to save in context switch More registers to save in context switch � Irregularity in CPI Irregularity in CPI � � MIPS64: 32 general- MIPS64: 32 general -purpose registers purpose registers 9 9 10 10 Memory Addressing Memory Addressing Little or Big: Where to Start? Little or Big: Where to Start? Instructions see registers, constant values, and memory Instructions see registers, constant values, and memory � Byte ordering: Byte ordering: � Where is the first Where is the first Number 0x5678 � Addressing mode Addressing mode decides how to specify an object to access decides how to specify an object to access � – – Object can be memory location, register, or a constant Object can be memory location, register, or a constant byte? byte? Little-endian Big-endian – Memory addressing is complicated – Memory addressing is complicated � Big Big- -endian endian : : IBM IBM, , � Memory addressing Memory addressing involves many factors involves many factors � � – – Memory addressing mode Memory addressing mode SPARC, SPARC, Mororola Mororola – – Object size Object size – – byte ordering byte ordering � Little Little- -endian: Intel, endian: Intel, � – alignment – alignment DEC DEC 00000003 5 8 For a memory location, its effective address For a memory location, its effective address is calculated in a is calculated in a � Supporting both: Supporting both: 00000002 6 7 certain form of register content, immediate address, and certain form of register content, immediate address, and � PC, as specified by the addressing mode PC, as specified by the addressing mode MIPS, PowerPC MIPS, PowerPC 00000001 7 6 00000000 8 5 11 11 12 12 2
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