Verilog HDL:Digital Design and Modeling Chapter 4 Expressions - PDF document

Chapter 4 Expressions 1 Verilog HDL:Digital Design and Modeling Chapter 4 Expressions

Chapter 4 Expressions 2 Page 120 //example of using a parameter module param1 (a, b, cin, sum); parameter width = 8; input [width-1:0] a, b; //a and b are 8 bits (7:0) input cin; //cin is a scalar output [width:0] sum; //sum is 9 bits (8:0) //to include cout //inputs default to wire reg [width:0] sum; always @ (a or b or cin) begin sum = a + b + cin; end endmodule Figure 4.2 Module for the 8-bit adder of Figure 4.1 illustrating the use of the pa- rameter statement. //param1 test bench module param1_tb; parameter width = 8; reg [width-1:0] a, b; reg cin; wire [width:0] sum; //display variables initial $monitor ("a b cin = %b_%b_%b, sum = %b", a, b, cin, sum); //continued on next page Figure 4.3 Test bench for the module of Figure 4.2.

Chapter 4 Expressions 3 //apply input vectors initial begin #0 a = 8'b0000_0011; b = 8'b0000_0100; cin = 1'b0; #5 a = 8'b0000_1100; b = 8'b0000_0011; cin = 1'b0; #5 a = 8'b0000_0111; b = 8'b0000_0110; cin = 1'b1; #5 a = 8'b0001_1001; //25 (19h) b = 8'b0010_0111; //39 (27h) cin = 1'b1; //1. sum = 65 (41h) #5 a = 8'b0111_1101; //125 (7dh) b = 8'b0110_0111; //103 (67h) cin = 1'b1; //1. sum = 229 (e5h) #5 a = 8'b1000_1111; //143 (8fh) b = 8'b1100_0110; //198 (c6h) cin = 1'b1; //1. sum = 342 (156h) #5 $stop ; end //instantiate the module into the test bench param1 inst1 ( .a(a), .b(b), .cin(cin), .sum(sum) ); endmodule Figure 4.3 (Continued)

Chapter 4 Expressions 4 Page 122 a b cin = 00000011_00000100_0, sum = 000000111 a b cin = 00001100_00000011_0, sum = 000001111 a b cin = 00000111_00000110_1, sum = 000001110 a b cin = 00011001_00100111_1, sum = 001000001 a b cin = 01111101_01100111_1, sum = 011100101 a b cin = 10001111_11000110_1, sum = 101010110 Figure 4.4 Outputs obtained from the test bench of Figure 4.3. Figure 4.5 Data analyzer waveforms for the test bench of Figure 4.4.

Chapter 4 Expressions 5 Page 128 //demonstrate arithmetic operations module arith_ops1 (a, b, opcode, rslt); input [3:0] a, b; input [2:0] opcode; output [7:0] rslt; reg [7:0] rslt; parameter addop = 3'b000, subop = 3'b001, mulop = 3'b010, divop = 3'b011, modop = 3'b100; always @ (a or b or opcode) begin case (opcode) addop: rslt = a + b; subop: rslt = a - b; mulop: rslt = a * b; divop: rslt = a / b; modop: rslt = a % b; default: rslt = 8’bxxxxxxxx; endcase end endmodule Figure 4.7 Verilog code illustrating the operations of addition, subtraction, multi- plication, division, and modulus. //arithmetic operations test bench module arith_ops1_tb; reg [3:0] a, b; reg [2:0] opcode; wire [7:0] rslt ; //continued on next page Figure 4.8 Test bench for the module of Figure 4.7.

Chapter 4 Expressions 6 initial $monitor ("a = %b, b = %b, opcode = %b, rslt = %b", a , b, opcode, rslt); initial begin #0 a = 4'b0011; b = 4'b0111; opcode = 3'b000; #5 a = 4'b1111; b = 4'b1111; opcode = 3'b001; #5 a = 4'b1110; b = 4'b1110; opcode = 3'b010; #5 a = 4'b1000; b = 4'b0010; opcode = 3'b011; #5 a = 4'b0111; b = 4'b0011; opcode = 3'b100; #5 $stop ; end //instantiate the module into //the test bench arith_ops1 inst1 ( .a(a), .b(b), .opcode(opcode), .rslt(rslt) ); endmodule Figure 4.8 (Continued) Page 129 a = 0011, b = 0111, opcode = 000, rslt = 00001010 //add a = 1111, b = 1111, opcode = 001, rslt = 00000000 //subtract a = 1110, b = 1110, opcode = 010, rslt = 11000100 //multiply a = 1000, b = 0010, opcode = 011, rslt = 00000100 //divide a = 0111, b = 0011, opcode = 100, rslt = 00000001 //modulus Figure 4.9 Outputs for the test bench of Figure 4.8.

Chapter 4 Expressions 7 Page 130 Figure 4.10 Waveforms for the test bench of Figure 4.8. Page 130 //examples of logical operators module log_ops1 (a, b, z1, z2, z3); input [3:0] a, b; output z1, z2, z3; assign z1 = a && b; assign z2 = a || b; assign z3 = !a; endmodule Figure 4.11 Examples of logical operators.

Chapter 4 Expressions 8 Page 131 //test bench for logical #5 a = 4'b0000; //operators b = 4'b0000; module log_ops1_tb; #5 a = 4'b1111; reg [3:0] a, b; b = 4'b1111; wire z1, z2, z3; #5 $stop ; initial end $monitor ("z1 = %d, z2 = %d, z3 = %d", z1, z2, z3); //instantiate the module //into the test bench //apply input vectors log_ops1 inst1 ( initial .a(a), begin .b(b), #0 a = 4'b0110; .z1(z1), b = 4'b1100; .z2(z2), .z3(z3) #5 a = 4'b0101; ); b = 4'b0000; endmodule #5 a = 4'b1000; b = 4'b1001; Figure 4.12 Test bench for the logical operators module. z1 = 1, z2 = 1, z3 = 0 //z1 is logical AND z1 = 0, z2 = 1, z3 = 0 //z2 is logical OR z1 = 1, z2 = 1, z3 = 0 //z3 is logical negation z1 = 0, z2 = 0, z3 = 1 z1 = 1, z2 = 1, z3 = 0 Figure 4.13 Outputs for the logical operators obtained from the test bench of Figure 4.12. Output z 1 is the logical AND; output z 2 is the logical OR; output z 3 is the logical negation.

Chapter 4 Expressions 9 Page 132 Figure 4.14 Waveforms for the logical operators obtained from the test bench of Figure 4.12. Output z 1 is the logical AND; output z 2 is the logical OR; output z 3 is the logical negation. Pagw 133 //examples of relational operators module relational_ops1 (a, b, gt, lt, gte, lte); input [3:0] a, b; output gt, lt, gte, lte; assign gt = a > b; assign lt = a < b; assign gte = a >= b; assign lte = a <= b; endmodule Figure 4.15 Verilog module to illustrate the relational operators.

Chapter 4 Expressions 10 Page 133 //test bench relational ops b = 4'b1001; module relational_ops1_tb; #5 a = 4'b0000; b = 4'b0000; reg [3:0] a, b; #5 a = 4'b1111; wire gt, lt, gte, lte; b = 4'b1111; #5 $stop ; initial end $monitor ("a=%b, b=%b, gt=%d, lt=%d, gte=%d, lte=%d", //instantiate the module a, b, gt, lt, gte, lte); relational_ops1 inst1 ( .a(a), //apply input vectors .b(b), initial .gt(gt), begin .lt(lt), #0 a = 4'b0110; .gte(gte), b = 4'b1100; .lte(lte) #5 a = 4'b0101; ); b = 4'b0000; endmodule #5 a = 4'b1000; Figure 4.16 Test bench for the relational operators module of Figure 4.15. Page 134 a=0110, b=1100, gt=0, lt=1, gte=0, lte=1 a=0101, b=0000, gt=1, lt=0, gte=1, lte=0 a=1000, b=1001, gt=0, lt=1, gte=0, lte=1 a=0000, b=0000, gt=0, lt=0, gte=1, lte=1 a=1111, b=1111, gt=0, lt=0, gte=1, lte=1 Figure 4.17 Outputs for the test bench of Figure 4.16 for the relational operators. Figure 4.18 Waveforms for the test bench of Figure 4.16 for the relational operators.

Chapter 4 Expressions 11 Page 135 //illustrate the use of equality operators module equality (x1, x2, x3, x4, x5, z1, z2, z3, z4); input [3:0] x1, x2, x3, x4, x5; output z1, z2, z3, z4; wire x1, x2, x3, x4, x5; //can be omitted. //inputs are wire by default //z1 is logical equality //z2 is logical inequality //z3 is case equality //z4 is case inequality reg z1, z2, z3, z4; always @ (x1 or x2 or x3 or x4 or x5) begin if (x1 == x2) //logical equality z1 = 1; else z1 = 0; end always @ (x1 or x2 or x3 or x4 or x5) begin if (x2 != x3) //logical inequality z2 = 1; else z2 = 0; end always @ (x1 or x2 or x3 or x4 or x5) begin if (x3 === x4) //case equality z3 = 1; else z3 = 0; end always @ (x1 or x2 or x3 or x4 or x5) begin if (x4 !== x5) z4 = 1; else z4 = 0; end endmodule Figure 4.19 Module to illustrate the use of the equality operators.

Chapter 4 Expressions 12 Page 136 //equality operators test bench module equality_tb; reg [3:0] x1, x2, x3, x4, x5; wire z1, z2, z3, z4; initial $monitor ("x1=%b, x2=%b, x3=%b, x4=%b, x5=%b, z1=%b, z2=%b, z3=%b, z4=%b", x1, x2, x3, x4, x5, z1, z2, z3, z4); //apply input vectors initial begin #0 x1 = 4'b1000; x2 = 4'b1101; x3 = 4'b01xz; x4 = 4'b01xz; x5 = 4'bx1xx; #10 x1 = 4'b1011; x2 = 4'b1011; x3 = 4'bx1xz; x4 = 4'bx1xz; x5 = 4'b11xx; #10 x1 = 4'b1100; x2 = 4'b0101; x3 = 4'bx10z; x4 = 4'b11xz; x5 = 4'b11xx; end //instantiate the module into the test bench equality inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .x5(x5), .z1(z1), .z2(z2), .z3(z3), .z4(z4) ); endmodule Figure 4.20 Test bench for the equality module of Figure 4.19.

Chapter 4 Expressions 13 Page 137 x1=1000, x2=1101, x3=01xz, x4=01xz, x5=x1xx, z1=0, z2=1, z3=1, z4=1 x1=1011, x2=1011, x3=x1xz, x4=x1xz, x5=11xx, z1=1, z2=1, z3=1, z4=1 x1=1100, x2=0101, x3=x01z, x4=11xz, x5=11xx, z1=0, z2=1, z3=0, z4=1 Figure 4.21 Outputs for the test bench of Figure 4.20 for the equality module of Fig- ure 4.19. Page 141 //example of the bitwise operators module bitwise1 (a, b, and_rslt, or_rslt, neg_rslt, xor_rslt, xnor_rslt); input [7:0] a, b; output [7:0] and_rslt, or_rslt, neg_rslt, xor_rslt, xnor_rslt; wire [7:0] a, b; reg [7:0] and_rslt, or_rslt, neg_rslt, xor_rslt, xnor_rslt; always @ (a or b) begin and_rslt = a & b; //bitwise AND or_rslt = a | b; //bitwise OR neg_rslt = ~a; //bitwise negation xor_rslt = a ^ b; //bitwise exclusive-OR xnor_rslt = a ^~ b; //bitwise exclusive-NOR end endmodule Figure 4.22 Module to illustrate the coding for the bitwise operators.