Verilog HDL:Digital Design and Modeling Chapter 6 User-Defined - PDF document

Chapter 6 User-Defined Primitives 1 Verilog HDL:Digital Design and Modeling Chapter 6 User-Defined Primitives

Chapter 6 User-Defined Primitives 2 Page 229 //3-input AND gate as a udp primitive udp_and3 (z1, x1, x2, x3);//output is listed first input x1, x2, x3; output z1; //state table table //inputs are in the same order as the input list // x1 x2 x3 : z1; comment is for readability 0 0 0 : 0; 0 0 1 : 0; 0 1 0 : 0; 0 1 1 : 0; 1 0 0 : 0; 1 0 1 : 0; 1 1 0 : 0; 1 1 1 : 1; endtable endprimitive Figure 6.1 A UDP for a 3-input AND gate. Page 231 //UDP for a 2-input AND gate primitive udp_and2 (z1, x1, x2); //output is listed first input x1, x2; output z1; //define state table table //inputs are the same order as the input list // x1 x2 : z1; comment is for readability 0 0 : 0; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive Figure 6.5 UDP for a 2-input AND gate.

Chapter 6 User-Defined Primitives 3 Page 231 //UDP for a 3-input OR gate primitive udp_or3 (z1, x1, x2, x3); //output is listed first input x1, x2, x3; output z1; //define state table table //inputs are the same order as the input list // x1 x2 x3 : z1; comment is for readability 0 0 0 : 0; 0 0 1 : 1; 0 1 0 : 1; 0 1 1 : 1; 1 0 0 : 1; 1 0 1 : 1; 1 1 0 : 1; 1 1 1 : 1; endtable endprimitive Figure 6.6 UDP for a 3-input OR gate. Page 232 //sum of products using udps for the AND gate and OR gate module udp_sop (x1, x2, x3, x4, z1); input x1, x2, x3, x4; output z1; //define internal nets wire net1, net2, net3; //instantiate the udps udp_and2 inst1 (net1, x1, x2); udp_and2 inst2 (net2, x3, x4); udp_and2 inst3 (net3, ~x2, ~x3); udp_or3 inst4 (z1, net1, net2, net3); endmodule Figure 6.7 Module for the sum-of-products logic of Figure 6.2 using UDPs.

Chapter 6 User-Defined Primitives 4 Page 232 //test bench for sum of products using udps module udp_sop_tb; reg x1, x2, x3, x4; wire z1; //apply input vectors initial begin : apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {x1, x2, x3, x4} = invect [4:0]; #10 $display ("x1x2x3x4 = %b, z1 = %b", {x1, x2, x3, x4}, z1); end end //instantiate the module into the test bench udp_sop inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .z1(z1) ); endmodule Figure 6.8 Test bench for the sum-of-products module of Figure 6.7.

Chapter 6 User-Defined Primitives 5 Page 233 x1x2x3x4 = 0000, z1 = 1 x1x2x3x4 = 1000, z1 = 1 x1x2x3x4 = 0001, z1 = 1 x1x2x3x4 = 1001, z1 = 1 x1x2x3x4 = 0010, z1 = 0 x1x2x3x4 = 1010, z1 = 0 x1x2x3x4 = 0011, z1 = 1 x1x2x3x4 = 1011, z1 = 1 x1x2x3x4 = 0100, z1 = 0 x1x2x3x4 = 1100, z1 = 1 x1x2x3x4 = 0101, z1 = 0 x1x2x3x4 = 1101, z1 = 1 x1x2x3x4 = 0110, z1 = 0 x1x2x3x4 = 1110, z1 = 1 x1x2x3x4 = 0111, z1 = 1 x1x2x3x4 = 1111, z1 = 1 Figure 6.9 Outputs for the test bench of Figure 6.8 for the sum-of-products module of Figure 6.7. Figure 6.10 Waveforms for the test bench of Figure 6.8 for the sum-of-products module of Figure 6.7.

Chapter 6 User-Defined Primitives 6 Page 236 //UDP for a 2-input NAND gate primitive udp_nand2 (z1, x1, x2); input x1, x2; output z1; //define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability 0 0 : 1; 0 1 : 1; 1 0 : 1; 1 1 : 0; endtable endprimitive Figure 6.14 UDP for a 2-input NAND gate. //UDP for a 3-input NAND gate primitive udp_nand3 (z1, x1, x2, x3); input x1, x2, x3; output z1; //define state table table //inputs are in the same order as the input list // x1 x2 x3 : z1; comment is for readability 0 0 0 : 1; 0 0 1 : 1; 0 1 0 : 1; 0 1 1 : 1; 1 0 0 : 1; 1 0 1 : 1; 1 1 0 : 1; 1 1 1 : 0; endtable endprimitive Figure 6.15 UDP for a 3-input NAND gate.

Chapter 6 User-Defined Primitives 7 Page 237 //UDP for a 4-input NAND gate primitive udp_nand4 (z1, x1, x2, x3, x4); input x1, x2, x3, x4; output z1; //define state table table //inputs are in the same order as the input list // x1 x2 x3 x4 : z1; comment is for readability 0 0 0 0 : 1; 0 0 0 1 : 1; 0 0 1 0 : 1; 0 0 1 1 : 1; 0 1 0 0 : 1; 0 1 0 1 : 1; 0 1 1 0 : 1; 0 1 1 1 : 1; 1 0 0 0 : 1; 1 0 0 1 : 1; 1 0 1 0 : 1; 1 0 1 1 : 1; 1 1 0 0 : 1; 1 1 0 1 : 1; 1 1 1 0 : 1; 1 1 1 1 : 0; endtable endprimitive Figure 6.16 UDP for a 4-input NAND gate.

Chapter 6 User-Defined Primitives 8 Page 237 //UDPs to design logic to activate segment a of an LED module udp_seg_a (x1, x2, x3, x4, z1); input x1, x2, x3, x4; output z1; //define internal nets wire net1, net2, net3, net4; udp_nand3 (net2, ~x1, x2, x4); udp_nand3 (net3, x1, ~x2, ~x3); udp_nand3 (net4, ~x2, ~x3, ~x4); udp_nand4 (z1, net1, net2, net3, net4); endmodule Figure 6.17 Module with UDPs to activate segment a of a 7 - segment LED. //test bench for udp_seg_a module udp_seg_a_tb; reg x1, x2, x3, x4; wire z1; initial //apply input vectors begin : apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {x1, x2, x3, x4} = invect [4:0]; #10 $display ("x1x2x3x4 = %b, z1 = %b", {x1, x2, x3, x4}, z1); end end //instantiate the module into the test bench udp_seg_a inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .z1(z1) ); endmodule Figure 6.18 Test bench for the module of Figure 6.17.

Chapter 6 User-Defined Primitives 9 Page 239 x1x2x3x4 = 0000, z1 = 1 x1x2x3x4 = 1000, z1 = 1 x1x2x3x4 = 0001, z1 = 0 x1x2x3x4 = 1001, z1 = 1 x1x2x3x4 = 0010, z1 = 1 x1x2x3x4 = 1010, z1 = 0 x1x2x3x4 = 0011, z1 = 1 x1x2x3x4 = 1011, z1 = 0 x1x2x3x4 = 0100, z1 = 0 x1x2x3x4 = 1100, z1 = 0 x1x2x3x4 = 0101, z1 = 1 x1x2x3x4 = 1101, z1 = 0 x1x2x3x4 = 0110, z1 = 1 x1x2x3x4 = 1110, z1 = 0 x1x2x3x4 = 0111, z1 = 1 x1x2x3x4 = 1111, z1 = 0 Figure 6.19 Outputs for the test bench of Figure 6.18 for the udp_seg_a module of Figure 6.17. The output values match the minterm entries in the Karnaugh map of Fig- ure 6.12. Figure 6.20 Waveforms for the test bench of Figure 6.18 for the udp_seg_a module of Figure 6.17.

Chapter 6 User-Defined Primitives 10 Page 242 //UDP for a 2-input exclusive-OR primitive udp_xor2 (z1, x1, x2); input x1, x2; output z1; //define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 0; endtable endprimitive Figure 6.22 UDP for an exclusive-OR function. //binary-to-Gray code converter using a UDP module bin_to_gray_udp (b3, b2, b1, b0, g3, g2, g1, g0); input b3, b2, b1, b0; output g3, g2, g1, g0; //instantiate the udps buf (g3, b3); udp_xor2 (g2, b3, b2); udp_xor2 (g1, b2, b1); udp_xor2 (g0, b1, b0); endmodule Figure 6.23 Module for a binary-to-Gray code converter using an exclusive - OR UDP.

Chapter 6 User-Defined Primitives 11 Page 243 //test bench for binary-to-Gray converter module bin_to_gray_udp_tb; reg b3, b2, b1, b0; wire g3, g2, g1, g0; //apply input vectors initial begin : apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {b3, b2, b1, b0} = invect [4:0]; #10 $display ("b3b2b1b0 = %b, g3g2g1g0 = %b", {b3, b2, b1, b0}, {g3, g2, g1, g0}); end end //instantiate the module into the test bench bin_to_gray_udp inst1 ( .b3(b3), .b2(b2), .b1(b1), .b0(b0), .g3(g3), .g2(g2), .g1(g1), .g0(g0) ); endmodule Figure 6.24 Test bench for the binary-to-Gray code converter of Figure 6.23. b3b2b1b0=0000, g3g2g1g0=0000 b3b2b1b0=1000, g3g2g1g0=1100 b3b2b1b0=0001, g3g2g1g0=0001 b3b2b1b0=1001, g3g2g1g0=1101 b3b2b1b0=0010, g3g2g1g0=0011 b3b2b1b0=1010, g3g2g1g0=1111 b3b2b1b0=0011, g3g2g1g0=0010 b3b2b1b0=1011, g3g2g1g0=1110 b3b2b1b0=0100, g3g2g1g0=0110 b3b2b1b0=1100, g3g2g1g0=1010 b3b2b1b0=0101, g3g2g1g0=0111 b3b2b1b0=1101, g3g2g1g0=1011 b3b2b1b0=0110, g3g2g1g0=0101 b3b2b1b0=1110, g3g2g1g0=1001 b3b2b1b0=0111, g3g2g1g0=0100 b3b2b1b0=1111, g3g2g1g0=1000 Figure 6.25 Outputs for the binary-to-Gray code converter of Figure 6.23.

Chapter 6 User-Defined Primitives 12 Page 246 //UDP for a 2-input exclusive-OR primitive udp_xor2 (z1, x1, x2); input x1, x2; output z1; //define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 0; endtable endprimitive Figure 6.28 Module for the udp_xor2 to be instantiated into the full adder module full_adder_udp . //full adder using a UDP and built-in primitives module full_adder_udp (a, b, cin, sum, cout); input a, b, cin; output sum, cout; //define internal nets wire net1, net2, net3; //instantiate the udps and built-in primitive udp_xor2 (net1, a, b); and inst1 (net2, a, b); udp_xor2 (sum, net1, cin); and inst2 (net3, net1, cin); or inst3 (cout, net3, net2); endmodule Figure 6.29 Module for a full adder using a UDP and built-in primitives.