Verilog HDL:Digital Design and Modeling Chapter 9 Structural - PDF document

Chapter 9 Structural Modeling 1 Verilog HDL:Digital Design and Modeling Chapter 9 Structural Modeling

Chapter 9 Structural Modeling 2 Page 492 //dataflow full adder module full_adder (a, b, cin, sum, cout); input a, b, cin; //list all inputs and outputs output sum, cout; wire a, b, cin; //define wires wire sum, cout; assign sum = (a ^ b) ^ cin; //continuous assignment assign cout = cin & (a ^ b) | (a & b); endmodule Figure 9.1 Module for a full adder showing the port list. //full adder test bench module full_adder_tb; reg a, b, cin; //inputs are reg for a test bench wire sum, cout; initial //apply input vectors begin : apply_stimulus reg [3:0] invect; for (invect = 0; invect < 8; invect = invect + 1) begin {a, b, cin} = invect [3:0]; #10 $display ("a b cin = %b, sum = %b, cout = %b", {a, b, cin}, sum, cout); end end //instantiate the module into the test bench full_adder inst1 ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) ); endmodule Figure 9.2 Test bench for the full adder module of Figure 9.1.

Chapter 9 Structural Modeling 3 Page 493 //behavioral D flip-flop module d_ff (d, clk, q, q_n, set_n, rst_n); input d, clk, set_n, rst_n; output q, q_n; wire d, clk, set_n, rst_n; reg q, q_n; always @ ( posedge clk or negedge rst_n or negedge set_n) begin if (rst_n == 0) begin q <= 1'b0; q_n <= 1'b1; end else if (set_n == 0) begin q <= 1'b1; q_n <= 1'b0; end else begin q <= d; q_n <= ~d; end end endmodule Figure 9.3 Behavioral module for a D flip-flop, where outputs q and q_n are declared as type reg .

Chapter 9 Structural Modeling 4 Page 496 //structural gray-to-binary converter module gray_to_bin_struc (g3, g2, g1, g0, b3, b2, b1, b0); input g3, g2, g1, g0; output b3, b2, b1, b0; wire g3, g2, g1, g0; wire b3, b2, b1, b0; assign b3 = g3; xor (b2, b3, g2); //instantiate the xor gates xor (b1, b2, g1); xor (b0, b1, g0); endmodule Figure 9.6 Structural module to convert a 4-bit Gray code to the corresponding bi- nary code. Page 497 //test bench for structural gray_to_bin converter module gray_to_bin_struc_tb; reg g3, g2, g1, g0; wire b3, b2, b1, b0; initial //apply input vectors and display variables begin : apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {g3, g2, g1, g0} = invect [4:0]; #10 $display ("{g3g2g1g0} = %b, {b3b2b1b0} = %b", {g3, g2, g1, g0}, {b3, b2, b1, b0}); end end gray_to_bin_struc inst1 ( //instantiate the module .g3(g3), .g2(g2), .g1(g1), .g0(g0), .b3(b3), .b2(b2), .b1(b1), .b0(b0) ); endmodule Figure 9.7 Test bench for the Gray-to-binary code converter of Figure 9.6.

Chapter 9 Structural Modeling 5 Page 497 g3g2g1g0=0000, b3b2b1b0=0000 g3g2g1g0=1000, b3b2b1b0=1111 g3g2g1g0=0001, b3b2b1b0=0001 g3g2g1g0=1001, b3b2b1b0=1110 g3g2g1g0=0010, b3b2b1b0=0011 g3g2g1g0=1010, b3b2b1b0=1100 g3g2g1g0=0011, b3b2b1b0=0010 g3g2g1g0=1011, b3b2b1b0=1101 g3g2g1g0=0100, b3b2b1b0=0111 g3g2g1g0=1100, b3b2b1b0=1000 g3g2g1g0=0101, b3b2b1b0=0110 g3g2g1g0=1101, b3b2b1b0=1001 g3g2g1g0=0110, b3b2b1b0=0100 g3g2g1g0=1110, b3b2b1b0=1011 g3g2g1g0=0111, b3b2b1b0=0101 g3g2g1g0=1111, b3b2b1b0=1010 Figure 9.8 Outputs for the Gray-to-binary code converter of Figure 9.6. Page 502 //bcd-to-decimal decoder module bcd_to_dec_struc (a, b, c, d, z0, z1, z2, z3, z4, z5, z6, z7, z8, z9); input a, b, c, d; output z0, z1, z2, z3, z4, z5, z6, z7, z8, z9; not (net1, a); not (net2, net1); not (net3, b); not (net4, net3); not (net5, c); not (net6, net5); not (net7, d); not (net8, net7); nand (z0, net1, net3, net5, net7); nand (z1, net1, net3, net5, net8); nand (z2, net1, net3, net6, net7); nand (z3, net1, net3, net6, net8); nand (z4, net1, net4, net5, net7); nand (z5, net1, net4, net5, net8); nand (z6, net1, net4, net6, net7); nand (z7, net1, net4, net6, net8); nand (z8, net2, net3, net5, net7); nand (z9, net2, net3, net5, net8); endmodule Figure 9.13 Module for a BCD-to-decimal decoder.

Chapter 9 Structural Modeling 6 Page 502 //structural module to use a bcd-to-dec decoder //to implement two functions f1 and f2 //and a bcd-to-excess-3 decoder module bcd_to_dec_apps (a, b, c, d, f1, f2, w, x, y, z); input a, b, c, d; output f1, f2, w, x, y, z; wire a, b, c, d; //define internal nets wire net0, net1, net2, net3, net4, net5, net6, net7, net8, net9; //instantiate the bcd-to-dec decoder bcd_to_dec_struc inst1 ( .a(a), .b(b), .c(c), .d(d), .z0(net0), .z1(net1), .z2(net2), .z3(net3), .z4(net4), .z5(net5), .z6(net6), .z7(net7), .z8(net8), .z9(net9) ); //instantiate the nand gates for functions f1 and f2 nand (f1, net1, net2, net4); nand (f2, net4, net7, net9); //instantiate the nand gates for bcd-to-excess-3 nand (w, net5, net6, net7, net8, net9); nand (x, net1, net2, net3, net4, net9); nand (y, net0, net3, net4, net7, net8); nand (z, net0, net2, net4, net6, net8); endmodule Figure 9.14 Structural module for the BCD-to-decimal decoder with applications.

Chapter 9 Structural Modeling 7 Page 503 //test bench for bcd-to-dec decoder with applications module bcd_to_dec_apps_tb; reg a, b, c, d; wire f1, f2, w, x, y, z; //apply stimulus and display variables initial begin : apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {a, b, c, d} = invect [4:0]; #10 $display ("abcd = %b, f1f2 = %b, wxyz = %b", {a, b, c, d}, {f1, f2}, {w, x, y, z}); end end //instantiate the module into the test bench bcd_to_dec_apps inst1 ( .a(a), .b(b), .c(c), .d(d), .f1(f1), .f2(f2), .w(w), .x(x), .y(y), .z(z) ); endmodule Figure 9.15 Test bench for the BCD-to-decimal decoder with applications.

Chapter 9 Structural Modeling 8 Page 504 abcd = 0000, f1f2 = 00, wxyz = 0011 abcd = 0001, f1f2 = 10, wxyz = 0100 abcd = 0010, f1f2 = 10, wxyz = 0101 abcd = 0011, f1f2 = 00, wxyz = 0110 abcd = 0100, f1f2 = 11, wxyz = 0111 abcd = 0101, f1f2 = 00, wxyz = 1000 abcd = 0110, f1f2 = 00, wxyz = 1001 abcd = 0111, f1f2 = 01, wxyz = 1010 abcd = 1000, f1f2 = 00, wxyz = 1011 abcd = 1001, f1f2 = 01, wxyz = 1100 abcd = 1010, f1f2 = 00, wxyz = 0000 abcd = 1011, f1f2 = 00, wxyz = 0000 abcd = 1100, f1f2 = 00, wxyz = 0000 abcd = 1101, f1f2 = 00, wxyz = 0000 abcd = 1110, f1f2 = 00, wxyz = 0000 abcd = 1111, f1f2 = 00, wxyz = 0000 Figure 9.16 Outputs for the BCD-to-decimal decoder with applications.

Chapter 9 Structural Modeling 9 Page 507 //behavioral jkff module jkff (clk, j, k, set_n, rst_n, q, q_n); input clk, j, k, set_n, rst_n; output q, q_n; wire clk, j, k, set_n, rst_n; reg q, q_n; always @ ( posedge clk or negedge set_n or negedge rst_n) begin if (~rst_n) begin q <= 1'b0; q_n <= 1'b1; end else if (~set_n) begin q <= 1'b1; q_n <= 1'b0; end else if (j==1'b0 && k==1'b1) begin q <= 1'b0; q_n <= 1'b1; end else if (j==1'b1 && k==1'b0) begin q <= 1'b1; q_n <= 1'b0; end else if (j==1'b1 && k==1'b1) begin q <= q_n; q_n <= q; end //continued on next page Figure 9.18 Behavioral module for a JK flip-flop.

Chapter 9 Structural Modeling 10 //The following else statement is not necessary, since the //state of the flip-flop will not change if all of the above //conditions are false; that is, j==1’b0 && k==1’b0 is not //necessary. However, it is inserted here for completeness. else begin q <= q; q_n <= q_n; end end endmodule Figure 9.18 (Continued) Page 509 //structural module for a modulo-10 counter using JK flip-flops module ctr_mod_10_jk_struc (set_n, rst_n, clk, y3, y2, y1, y0); input set_n, rst_n, clk; output y3, y2, y1, y0; //define internal nets wire set_n, rst_n, clk; wire net1, net2, net3, net4; //instantiate the logic primitive and the JK flip-flop for y3 and (net1, y2, y1, y0); jkff inst3 ( .clk(clk), .j(net1), .k(y0), .set_n(set_n), .rst_n(rst_n), .q(y3) ); //continued on next page Figure 9.19 Structural module for a modulo-10 counter using JK flip-flops.

Chapter 9 Structural Modeling 11 //instantiate the logic primitives and the JK flip-flop for y2 and (net2, y0, y1, ~y3); and (net3, y0, y1); jkff inst2 ( .clk(clk), .j(net2), .k(net3), .set_n(set_n), .rst_n(rst_n), .q(y2) ); //instantiate the logic primitive and the JK flip-flop for y1 and (net4, y0, ~y3); jkff inst1 ( .clk(clk), .j(net4), .k(y0), .set_n(set_n), .rst_n(rst_n), .q(y1) ); //instantiate the logic primitive and the JK flip-flop for y0 jkff inst0 ( .clk(clk), .j(1'b1), .k(1'b1), .set_n(set_n), .rst_n(rst_n), .q(y0) ); endmodule Figure 9.19 (Continued)

Chapter 9 Structural Modeling 12 Page 510 //test bench for the structural modulo-10 counter //using JK flip-flops module ctr_mod_10_jk_struc_tb; reg set_n, rst_n, clk; wire y3, y2, y1, y0; //display variables initial $monitor ("y3y2y1y0 = %b", {y3, y2, y1, y0}); //generate reset initial begin #0 set_n = 1'b1; rst_n = 1'b0; #5 rst_n = 1'b1; end //generate clock initial begin clk = 1'b0; forever #10 clk = ~clk; end //determine length of simulation initial begin repeat (11) @ ( posedge clk); $stop ; end //instantiate the module ctr_mod_10_jk_struc inst1 ( .set_n(set_n), .rst_n(rst_n), .clk(clk), .y3(y3), .y2(y2), .y1(y1), .y0(y0) ); endmodule Figure 9.20 Test bench for the modulo-10 counter using JK flip-flops.