Verilog HDL:Digital Design and Modeling Chapter 3 Keywords Chapter - PDF document

Chapter 3 Keywords 1 Verilog HDL:Digital Design and Modeling Chapter 3 Keywords

Chapter 3 Keywords 2 Page 80 //4:1 multiplexer using a always @ (sel or data) //case statement begin module mux_4_1_case (sel, case (sel) data, out); (0) : out = data[0]; (1) : out = data[1]; input [1:0] sel; (2) : out = data[2]; input [3:0] data; (3) : out = data[3]; output out; endcase end reg out; endmodule Figure 3.3 Multiplexer design using a case statement. Page 81 //example of defparam //define top level module module def_param1; //for defparam1 module top_level; parameter x1 = 0; defparam value1.x1 = 4; initial defparam value2.x1 = 8; $display ("value=%d", x1); def_param1 value1 ( ); endmodule def_param1 value2 ( ); (a) endmodule (b) value = 8 value = 4 value = 0 (c) Figure 3.4 Verilog code to illustrate the use of the defparam keyword: (a) param- eter keyword, (b) defparam keyword to change the value, and (c) the outputs.

Chapter 3 Keywords 3 Page 86 //example of the repeat keyword module repeat_example; integer count; initial begin count = 0; repeat (8) begin $display ("count = %d", count); count = count + 1; end end endmodule Figure 3.5 Example of the repeat keyword for loop control. count = 0 count = 4 count = 1 count = 5 count = 2 count = 6 count = 3 count = 7 Figure 3.6 Outputs for the Verilog code of Figure 3.5.

Chapter 3 Keywords 4 Page 88 //illustrates the use of the while statement module while_example; integer count; initial begin count = 0; while (count < 16) begin $display ("count = %d", count); count = count + 1; end end endmodule Figure 3.7 Example of the while keyword for loop control. Page 89 count = 0 count = 4 count = 8 count = 12 count = 1 count = 5 count = 9 count = 13 count = 2 count = 6 count = 10 count = 14 count = 15 count = 3 count = 7 count = 11 Figure 3.8 Outputs for the Verilog code of Figure 3.7.

Chapter 3 Keywords 5 Page 91 //example of specify block with delays module specify_block (x1, x2, z1); input x1, x2; output z1; nor (z1, x1, x2); specify specparam tplh = 0.55 : 0.90 : 1.20, //min : typ : max tphl = 0.50 : 0.70 : 1.55; (x1 => z1) = tplh, tphl; (x2 => z1) = tplh, tphl; endspecify endmodule Figure 3.10 Example of a specify block. Page 96 //used-defined primitive for a 2-input OR gate primitive udp_or2 (out, a, b); //list output first //declarations output out; //must be output (not reg) //for comb logic input a, b; //state table definition table //inputs are in same order as input list // a b : out; comment is for readability 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 1; endtable endprimitive Figure 3.12 A UDP for a 2-input OR gate.

Chapter 3 Keywords 6 Page 98 //module showing use of wire and inst1 (net1, x1, ~x2); //connecting logic primitives and inst2 (net2, ~x1, x2); not inst3 (net3, ~x3); module log_diag_eqn4 (x1, x2, or inst4 (net4, net1, net2); x3, z1, z2); or inst5 (net5, net2, net3); input x1, x2, x3; assign z1 = net4; output z1, z2; assign z2 = net5; wire x1, x2, x3; endmodule wire z1, z2; //define internal nets as wire wire net1,net2,net3,net4,net5; //instantiate the built-in //primitives Figure 3.14 Module showing the use of wires to connect logic primitives. Page 99 //logic diagram test bench #10 x1=1'b1; x2=1'b0; x3=1'b0; module log_diag_eqn4_tb; #10 x1=1'b1; x2=1'b0; x3=1'b1; #10 x1=1'b1; x2=1'b1; x3=1'b0; reg x1, x2, x3; #10 x1=1'b1; x2=1'b1; x3=1'b1; wire z1, z2; #10 $stop ; end //display variables initial //instantiate the module into $monitor ("x1x2x3 = %b, //the test bench z1 = %b, z2 = %b", log_diag_eqn4 inst1 ( {x1, x2, x3}, z1, z2); .x1(x1), .x2(x2), //apply stimulus .x3(x3), initial .z1(z1), begin .z2(z2) #0 x1=1'b0; x2=1'b0; x3=1'b0; ); #10 x1=1'b0; x2=1'b0; x3=1'b1; #10 x1=1'b0; x2=1'b1; x3=1'b0; endmodule #10 x1=1'b0; x2=1'b1; x3=1'b1; Figure 3.15 Test bench for the module of Figure 3.14.

Chapter 3 Keywords 7 Page 99 x1x2x3 = 000, z1 = 0, z2 = 0 x1x2x3 = 100, z1 = 1, z2 = 0 x1x2x3 = 001, z1 = 0, z2 = 1 x1x2x3 = 101, z1 = 1, z2 = 1 x1x2x3 = 010, z1 = 1, z2 = 1 x1x2x3 = 110, z1 = 0, z2 = 0 x1x2x3 = 011, z1 = 1, z2 = 1 x1x2x3 = 111, z1 = 0, z2 = 1 Figure 3.16 Binary outputs for the module of Figure 3.14. Figure 3.17 Waveforms for the test bench of Figure 3.15.

Chapter 3 Keywords 8 Page 105 //procedure for loading memory with //binary data from file icache.instr module mem_load (pc, ic_data_out); //list inputs and outputs input pc; output ic_data_out; //list wire and reg wire [2:0] pc; //a program counter to address 8 words reg [7:0] ic_data_out; //define memory size //instr_cache is an array of eight 8-bit regs reg [7:0] instr_cache [0:7]; //define memory contents //load instr_cache from file icache.instr initial begin $readmemb ("icache.instr", instr_cache); end //use a program counter to access the instr_cache always @ (pc) begin ic_data_out = instr_cache [pc]; end endmodule Figure 3.12 Verilog module to illustrate the use of $readmemb to load an instruc- tion cache.

Chapter 3 Keywords 9 Page 106 //mem_load test bench module mem_load_tb; integer i;//used to display contents reg [2:0] pc; wire [7:0] ic_data_out; //assign values to the program counter initial begin #0 pc = 3'b000; #10 pc = 3'b001; #10 pc = 3'b010; #10 pc = 3'b011; #10 pc = 3'b100; #10 pc = 3'b101; #10 pc = 3'b110; #10 pc = 3'b111; #15 $stop ; end //display the contents of the instruction cache initial begin for (i=0; i<8; i=i+1) begin #10 $display ("address %h = %b", i, ic_data_out); end #150 $stop ; end //instantiate the module into the test bench mem_load inst1 ( .pc(pc), .ic_data_out(ic_data_out) ); endmodule Figure 3.22 Test bench for the module of Figure 3.21.

Chapter 3 Keywords 10 Page 107 0000_1000 0000_1001 0000_1010 0000_1011 0000_1100 0000_1101 0000_1110 0000_1111 Figure 3.23 Instruction cache file icache.instr saved as a separate file. It is saved in the project folder without the .v extension. address 00000000 = 00001000 address 00000004 = 00001100 address 00000001 = 00001001 address 00000005 = 00001101 address 00000002 = 00001010 address 00000006 = 00001110 address 00000003 = 00001011 address 00000007 = 00001111 Figure 3.24 Outputs obtained from the test bench of Figure 3.22. Page 108 Figure 3.25 Waveforms for the test bench of Figure 3.22.