Introduction to Digital VLSI Design VLSI יתרפס� ��ונכתל�אובמ Verilog – Logic Synthesis with Verilog HDL Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel 09/03/07 1
Objectives � Define logic synthesis and explain the benefits of logic synthesis � Identify Verilog HDL constructs and operators accepted in logic synthesis. Understand how the logic synthesis tool interprets these constructs � Explain the typical design flow, using logic synthesis. Describe the components in the logic synthesis-based design flow � Describe verification of the gate-level netlist produced by logic synthesis � Understand techniques for writing efficient RTL description � Describe partitioning techniques to help logic synthesis provide the optimal gate-level netlist � Design combinational and sequential circuits, using logic synthesis Introduction to Digital VLSI 09/03/07 2 Gil Rahav Freescale Semiconductor Israel
Impact of Logic Synthesis � Logic synthesis always existed even in the days of schematic gate- level design, but it was always done inside the designer’s mind � For large design, manual conversion was prone to human error � The designer could never be sure that the design constraints were going to be met until the gate-level implementation was completed and tested � A significant portion of the design-cycle was dominated by the time taken to convert a high-level design into gates � The turnaround time for redesign of blocks was very high � What-if scenarios were hard to verify � Each designer would implement design blocks differently � If a bug was found in the final, gate-level design, this would sometimes require redesign of thousands of gates � Timing, area, and power dissipation in library cells are fabrication- technology specific � Design reuse was not possible (technology specific, hard to port, …) Introduction to Digital VLSI 09/03/07 3 Gil Rahav Freescale Semiconductor Israel
Impact of Logic Synthesis � The advent of computer-aided logic synthesis tools has automated the process of converting the high-level description to logic gates � High-level design is less prone to human error � High-level design is done without significant concern about design constraints � Conversion from high-level design to gates is fast � Turnaround time for redesign of blocks is shorter � What-if scenarios are easy to verify � Logic synthesis tools optimize the design as a whole � If a bug was found in the final, gate-level design, the designer goes back and changes the high-level description to eliminate the bug � Logic synthesis tools allow technology-independent design � Design reuse is possible for technology-independent descriptions Introduction to Digital VLSI 09/03/07 4 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis � For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL) � The term RTL is used for an HDL description style that utilizes a combination of dataflow and behavioral constructs � Verilog and VHDL are the two most popular HDLs used to describe the functionality at the RTL level � Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level netlist � RTL-based synthesis is currently the most popular design method Introduction to Digital VLSI 09/03/07 5 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Verilog Constructs � In general, any construct that is used to define a cycle-by-cycle RTL description is acceptable to the logic synthesis tool Construct Type Keyword of Description Notes ports input, inout, output parameters parameter module definition module signals & variables wire, reg, tri Vectors are allowed instantiation module & primitive instances mymux m1(out, i0, i2, s); nand (out, a, b); functions & tasks function, task Timing constructs ignored procedural always, if, then, else, case(x/z) initial is not supported procedural blocks begin, end, named blocks, disable Disabling of named blocks allowed data flow assign Delay information is ignored while and forever loops must contain loops for, while, forever @(posedge clk) or @(negedge clk) Introduction to Digital VLSI 09/03/07 6 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Think Hardware!!! � Remember that we are providing a cycle-by-cycle RTL description of the circuit � There are restrictions on the way these constructs are used for the logic synthesis tool. For example: � The while and forever loops must be broken by a @(posedge clock) or @(negedge clock) statement to enforce cycle-by-cycle behavior and to prevent combinational feedback � Logic synthesis ignores all timing delays specified by #<delay> construct. Therefore, pre- and post-synthesis Verilog simulation results may not match. The designer must use a description style that eliminates these mismatches � The initial construct is not supported by logic synthesis tools. Instead, the designer must use a reset mechanism to initialize the signals in the circuit � … Introduction to Digital VLSI 09/03/07 7 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Timing Delays � Pre- and post-synthesis Verilog simulation results may not match � Logic synthesis ignores all timing module code11 (out1, out2, in); module code11 (out1, out2, in); delays specified by #<delay> output out1, out2; output out1, out2; construct input in; input in; reg out1, out2; reg out1, out2; � In RTL simulation the outputs will always @(in) always @(in) not be updated on every input (in begin begin signal) change if changes happen #25 out1 = ~in; #25 out1 = ~in; #40 out2 = ~in; more frequently than the delay in #40 out2 = ~in; end end the logic (65 time units in the endmodule endmodule example) � The designer must use a description style that eliminates these mismatches Introduction to Digital VLSI 09/03/07 8 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Verilog Operators � Almost all operators in Verilog are allowed for logic synthesis Operators Type Operator Symbol Operation Performed Arithmetic * / + - % Multiply, divide, add, subtract, modulus Logical ! && || Logical negation, and, or Greater than, Less than, Greater than or equal Relational > < >= <= to, Less than or equal to Equality == != Equality, inequality Bit-wise ~ & | ^ ~^ ^~ Bitwise negation, and, or, nor, xor, xnor Reduction & ~& | ~| ^ ~^ ^~ Reduction and, nand, or, nor, xor, xnor Shift << >> Left shift, right shift Concatenation { } Concatenation Conditional ?: Conditional � Only operators such as “===“ and “!==“ that are related to “x” and “z” are not allowed (equality with “x” and “z” does not have much meaning in logic synthesis) Introduction to Digital VLSI 09/03/07 9 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Top-Down Design � Model entire system architecturally, in Requirements Analysis Requirements Analysis Verilog or some other high-level language � Partition your design based on functionality System Partitioning System Partitioning or path length Behavioral/Functional Behavioral/Functional � Write a behavioral Verilog model for each Specification Specification partition as an executable bus-functional specification of the design Behavioral/Functional Behavioral/Functional � Write or generate the same models at the Verification Verification RTL level, using synthesizable constructs. Assemble and verify entire RTL system � Translate the functional models to gate- Synthesis & Optimization Synthesis & Optimization level netlists using synthesis and optimization tool � Mixed-level logic simulation allows you to Gate Level Verification Gate Level Verification verify the design at all levels Introduction to Digital VLSI 09/03/07 10 Gil Rahav Freescale Semiconductor Israel
Verilog HDL Synthesis: Design Partitioning � Design partitioning is another important factor for efficient logic synthesis � The way the designer partitions the design can greatly affect the output of the logic synthesis tool � Various partitioning techniques can be used � Hierarchical partitioning � Horizontal partitioning � Vertical partitioning � Parallelizing design structure Introduction to Digital VLSI 09/03/07 11 Gil Rahav Freescale Semiconductor Israel
Hierarchical Design Partitioning � Module statements create hierarchical design blocks (see part III of this course) � Continuous assignments (assigns) and procedural blocks (always) do not create hierarchy ADR_BLK module ADR_BLK (. . .); module ADR_BLK (. . .); Dec DEC U1 (ADR, CLK, INST); DEC U1 (ADR, CLK, INST); OK U2 (ADR, CLK, AS, OK); OK U2 (ADR, CLK, AS, OK); endmodule; endmodule; Ok Introduction to Digital VLSI 09/03/07 12 Gil Rahav Freescale Semiconductor Israel
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