CS/EE 6710 CS/EE 6710 Digital VLSI Design Digital VLSI Design CS/EE 6710 CS/EE 6710 � Digital VLSI Design � Web Page - all sorts of information! � T Th 12:25-1:45, LCB 219 � http://www.cs.utah.edu/classes/cs6710 � Instructor: Prof. Erik Brunvand � Contact: � MEB 3142 � cs6710@cs.utah.edu � Office hours: After class, or by appointment � TA: Vamshi Kadaru � Goes to everyone in the class � You need to sign up – go to � Office hours: In the CADE lab – times TBD http://mailman.cs.utah.edu/mailman/listinfo/cs6710 � teach-cs6710@cs.utah.edu � Goes to instructor and TAs Textbook Secondary Textbook � My draft lab � Principles of manual for our CMOS VLSI CAD flow Design � Available on the class web site in Weste and Harris PDF as chapters become available (3 nd edition) � 1
Class Goal Class Goal � To learn about modern � We’ll use tools from digital CMOS IC design Cadence and Synopsys � Class project – � These only run on Solaris and Linux in the CADE teams will build moderate sized chip lab, so you’ll need a CADE account � We’ll form teams in a few weeks � I also assume you know something about UNIX � Modulo funding constraints, these chips can be � http://www.cs.utah.edu/classes/cs1010/ fabricated through MOSIS � Chip fabrication service for small-volume projects � Educational program funded entirely by MOSIS Prerequisites Assignment #1 – Review � On the class web site is a review assignment � Digital design is required! (i.e. CS/EE 3700) � If you can do these problems, you probably have � Boolean algebra the right background � Combinational circuit design and optimization � If you can’t, you will struggle!!!!! � K-map minimization, SOP, POS, DeMorgan, � Please take this seriously! Give this exam a bubble-pushing, etc. try and make sure you remember what you � Arithmetic circuits, 2’s complement numbers need to know! � Sequential Circuit design and optimization � You also need to turn it in next week by � Latch/flip-flop design Friday September 1 st � Finite state machine design/implementation � Grading is pass/fail � Communicating FSMs � Using FSMs to control datapaths Recommendations First Assignment � Computer Architecture experience is helpful � CAD Assignment #1 � Instruction set architecture (ISA) � Cadence Composer tutorial � Assembly language execution model � Simple circuit design with simulation � Instruction encoding � Learn basic Verilog for testbench � Simple pipelining � Available on the web site � I assume you’ve used some sort of CAD tools � Due on Friday, September 1 st , 5:00pm for digital circuits � Schematic capture � Simulation � 2
Assignments/Grading The Big Picture � Labs (cell designs) & Homework (40%) � Design review (5%) Logic Gates Physics Electronics VLSI � Mid-term exam (15%) � Final Project (40%) FSM � See the syllabus (web page) for more details FSM RTL Computer about grading breakdown OS M OV R1 R2 if (c==1) Compilers ADD R1 R3 R5 x = foo(y); else ST R3 (5)R6 x = bar(a,b); Algorithms Progamming I SA Applications Languages Etc... Lightening Tour of VLSI Design VLSI Design � Or start with a schematic (or a mix of both) � Start with HDL program (VHDL, Verilog) entity traffic is port (CLK, go_green, go_red, go_yellow: in STD_LOGIC; -- when others => l_green, l_red, l_yellow: out STD_LOGIC;); null; end; end case; architecture traffic_arch of traffic is end if; -- SYMBOLIC ENCODED state machine: Sreg0 end process; type Sreg0_type is (green, red, yellow); assignment statements for combinatorial outputs signal Sreg0: Sreg0_type; l_green_assignment: begin l_green <= '1' when (Sreg0 = green) else --concurrent signal assignments '0' when (Sreg0 = red) else Sreg0_machine: process (CLK) '0' when (Sreg0 = yellow) else begin '0'; if CLK'event and CLK = '1' then case Sreg0 is l_yellow_assignment: when green => l_yellow <= '0' when (Sreg0 = green) else if go_yellow='1' then '0' when (Sreg0 = red) else Sreg0 <= yellow; '1' when (Sreg0 = yellow) else end if; '1'; when red => if go_green='1' then l_red_assignment: Sreg0 <= green; l_red <= '0' when (Sreg0 = green) else end if; '1' when (Sreg0 = red) else when yellow => '0' when (Sreg0 = yellow) else if go_red='1' then '0'; Sreg0 <= red; end if; end traffic_arch; Convert Gates to Transistors Convert Transistors to Layout � 3
Assemble Gates into a Circuit And Assemble Whole Chip Example Class Chip (2001) Same Chip (no M2, M3) 1.5mm x 3.0mm, 72 I/O pads 16-bit Processor, approx 27,000 transistors Zoom In… Zoom In… A Hair (100 microns) � 4
Another Class Project (2001) Standard-Cell Part 3.0mm x 3.0mm 84 I/O Pads Standard-Cell Zoom Register File Adder/Shifter Class project from 2002 16-bit CORDIC Processor � 5
Class project from 2003 Class project from 2003 Basketball Scoreboard Display Basketball Scoreboard Display Another class project (2003) Class project from 2005 Simple processor (+, -, *, /) with Bomb game ADC on the input With VGA output Bomb game from 2005 Bomb game from 2005 � 6
Fabricate and Test the Chip IC Technology � We can fabricate the chips through MOSIS � We’ll use the AMI 0.6u 3-level-metal � Educational program sponsored by MOSIS’ commercial CMOS process activities � We have technology files that define the process � Chips are fabricated, packaged, and shipped back to us � MOSIS Scalable CMOS Rev. 8 (SCMOS) � Then we get to test them to see what they do, or � Tech files from NCSU CDK don’t do… � NCSU toolkit is designed for custom VLSI layout � Not necessarily a research area in its own right here � Design Rule Check (DRC) rules at Utah � Layout vs. Schematic (LVS) rules � But, a powerful tool for hardware-related research projects! Class Project Class Project � Two complete design views: � Standard Cell Library Schematic and Layout � Each group will design a small, but useful, � Complete design in Composer schematics, standard cell library simulated with Verilog � Use HDL synthesis with this library as a target � Complete design at layout level in Virtuoso with � Use Cadence SOC Encounter for place and route detailed simulation using Spectre � Custom Datapath � Validate they are the same with LVS � Custom layout for datapath � Use ICC router to connect HDL-Synthesized control to custom-designed datapath � Synthesized controller using Synopsys, SOC � It will be VERY helpful to have a mix of Encounter, and your cell library knowledge on your team � Final assembly back in Virtuoso Timetable A View of the Tools Verilog-XL � This project will be a race to the finish! Synopsys Behavioral � There is no slack in this schedule!!! Synthesis Verilog � VLSI design always takes longer than you think Structural Verilog � Even if you take that rule into account! Cadence Your � After you have 90% finished, SOC Encounter Library there’s only 90% left… Circuit Verilog-XL Spectre � All team members will have to contribute! CSI Layout � Team peer evaluations twice a semester Cadence Cadence LVS AutoRouter Virtuoso Composer (SOC or ccar) Layout-XL Layout Schematic � 7
A View of the Tools A View of the Tools Verilog-XL Verilog-XL Synopsys Synopsys Behavioral Behavioral Synthesis Synthesis Verilog Verilog Structural Structural Verilog Verilog Cadence Cadence Your Your SOC Encounter SOC Encounter CAD1 CAD2 Library Library Circuit Circuit Verilog-XL Verilog-XL Spectre Spectre CSI CSI Layout Layout Cadence Cadence Cadence Cadence LVS LVS AutoRouter AutoRouter Virtuoso Composer Virtuoso Composer (SOC or ccar) (SOC or ccar) Layout-XL Layout-XL Layout Schematic Layout Schematic Cadence Composer Schematic Cadence Composer Schematic Cadence Composer Symbol Cadence Virtuoso Layout � 8
Standard Cells…Power Rings Place Cells and Fillers Connect Rows to Power autoRouted View autoRouted Layout View Corners… � 9
Routing Slightly Larger Example Electronics Summary Reminder: Voltage Division � Voltage is a measure of electrical potential energy � Find the voltage across any series-connected � Current is moving charge caused by voltage resistors � Resistance reduces current flow � Ohm’s Law: V = I R Energy (joules): work required to � Power is work over time move one coulomb of charge by one volt or work done to produce one watt � P = V I = I 2 R = V 2 /R for one sec � Capacitors store charge � It takes time to charge/ discharge a capacitor � Time to charge/discharge is related exponentially to RC � It takes energy to charge a capacitor � Energy stored in a capacitor is (1/2)CV 2 Example of Voltage Division Example of Voltage Division � Find the voltage at point A with respect to � Find the voltage at point A with respect to GND GND � 10
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