VLSI VLSI - Digital Signal Processing Digital Signal Processing - - - 張錫嘉 Hsie-Chia Chang E-mail : hcchang@mail.nctu.edu.tw Fall 2006
Course I nformation Course I nformation � Mission – This course will cover the most important methodologies to map DSP algorithms into VLSI efficiently. Several high-level algorithm and architecture design techniques will be introduced to optimize performance (i.e. area 、 speed 、 power 、 roundoff noise) � Text book – Keshab K. Parhi, VLSI Digital Signal Processing Systems , Wiley, 1999 � Reference – M. Mehendale and S. D. Sherlekar, VLSI Synthesis of DSP Kernels , Kluwer Academic Publishers, 2001 – Ray Liu, High-Performance VLSI Signal Processing , IEEE Press, 1998 – S. Y. Kung, VLSI Array Processors , Prentice-Hall Internationak, 1988 Optimized Application-Specific I ntegrated Systems 2
Related Course Related Course 基礎課程 ( 大一、大二 計算機概論 邏輯設計 計算機程式設計 電子學、電路學 ) 數位電路與系統 資料結構 工程數學 核 ( 大三、大四 計算機組織 心 通訊原理 VLSI 設計導論 數位訊號處理 課 IC LAB(I)(II) 程 ) 數位積體電路設計 類比積體電路設計 進階課程 數位通訊 電腦輔助設計 SOC 設計概論 混合訊號積體電路設計測試 VLSI 訊號處 高等數位訊號處理 理架構設計 射頻積體電路設計 Optimized Application-Specific I ntegrated Systems 3
Course Content (1/ 3) Course Content (1/ 3) � High-level Architectural Transformation – Iteration Bound Chap. 2 – Pipelining and Parallel Processing Chap. 3 – Retiming Chap. 4 – Unfolding Chap. 5 – Folding Chap. 6 – Systolic Architecture Design Chap. 7 � High-level algorithm Transformation – Fast Convolution Chap. 8 – Algorithm Strength Reduction in Filters and Transforms Chap. 9 – Pipelined and Parallel Recursive and Adaptive Filter Chap. 10 – Scaling and Roundoff Noise Chap. 11 – Digital Lattice Filter Structures Chap. 12 Optimized Application-Specific I ntegrated Systems 4
Course Content (2/ 3) Course Content (2/ 3) � High-performance VLSI architecture & systems – Bit-level Arithmetic Architectures Chap. 13 – Redundant Arithmetic Chap. 14 – Numerical Strength Reduction Chap. 15 – Synchronous, Wave, and Asynchronous Pipelines Chap. 16 – Low-Power Design Chap. 17 – Programmable Digital Signal Processors Chap. 18 � Appendix – Shortest Path Algorithms 、 Scheduling and Allocation Techniques – Euclidean GCD Algorithm 、 Orthonormality of Schur Polynomials – Fast Binary Adders and Multipliers 、 Scheduling in Bit-Serial Systems – Coefficient Quantization in FIR Filters Optimized Application-Specific I ntegrated Systems 5
Course Content (2/ 3) Course Content (2/ 3) � Lecture 01: Overview Chap. 1, 2 � Lecture 02: Pipelining & Retiming Chap. 3, 4 � Lecture 03: Unfolding Transformation Chap. 5 � Lecture 04: Folding Transformation Chap. 6 � Case Study I : 2D-ACS Unit for Viterbi Decoders � Lecture 05: Systolic Arrays Chap. 7 � Lecture 06: Algorithmic Strength Reduction Chap. 9 � Case Study I I : FFT Processors � Lecture 07: Bit-Serial Architectures Chap. 13 (I ) � Lecture 08: Redundant Arithmetic Chap. 14 � Lecture 09: Numerical Strength Reduction Chap. 15 � Lecture 10: Distributed Arithmetic Chap. 13 (I I ) Optimized Application-Specific I ntegrated Systems 6
Course Content (3/ 3) Course Content (3/ 3) � Grading – Homework + Project report 40% – Midterm exam. 30% – Final exam. 30% � Final Project – The project can be individual project or a group project – Project type can be either theory/algorithm development or implementation – Project report is required to be submitted before the end of this semester – Project presentation will take place in class � Teaching Assistant – 郭羽庭 ED412, 5712121 ext.54225, ytkuo@twins.ee.nctu.edu.tw – ??? � Course Website – http://oasis2.ee.nctu.edu.tw/VLSI_DSP Optimized Application-Specific I ntegrated Systems 7
Typical DSP Algorithm Typical DSP Algorithm 熟悉 普通 沒聽過 Convolution 13 32 Digital Filters 39 Adaptive Filters 8 24 Motion Estimation 2 17 20 Discrete Cosine Transform 41 Vector Quantization 10 30 Viterbi Algorithm` 26 8 Decimator and Expander 30 8 深 廣 Wavelets and Filter Banks 16 21 19 14 FFT 2 25 Optimized Application-Specific I ntegrated Systems 8
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