Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications Paul Muller Microelectronic Systems Lab (LSM) École Polytechnique Fédérale de Lausanne (EPFL)
Contributors • Matthew K. Emsley and Prof. M. Selim Ünlü Boston University Photonics Center Boston, MA, USA • Armin Tajalli, visiting Ph.D. student Sharif University of Technology Teheran, Iran • Prof. Yusuf Leblebici, Ph.D. thesis advisor École Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 2
Motivation (1/2) CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 3
Motivation (2/2) • Transistor count grows exponentially (Moore) • I/O count grows with perimeter (Rent) CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 4
Current Server Interconnects • Electrical and Optical Silicon Graphics Inc., Web Site L.Buckman et al. , Parallel Optical Interconnects, CLEO 2000 CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 5
Next-Generation Chip-to-Chip Links H.Takahara, Optoelectronic Packaging Trends in Japan , Stanford University, US-Asia TMC, May 2003 CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 6
Outline • Motivation • Particularities of Short-Distance Links • Pure Silicon Photodetectors • Transimpedance and Limiting Amplifier Design • Gated Oscillator CDR • Conclusion CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 7
Outline • Motivation • Particularities of Short-Distance Links • Pure Silicon Photodetectors • Transimpedance and Limiting Amplifier Design • Gated Oscillator CDR • Conclusion CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 8
Optical Receiver Overview Traditionally BiCMOS CLK InGaAs TIA LA CDR DATA CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 9
Optical Receiver Overview Si CMOS CLK TIA LA CDR DATA All in CMOS CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 10
Multi-Channel Requirements • Low cost – Standard CMOS (at least compatible) – Low area (no inductors?) • Low power (inductors?) • Designed for use as IP – Simple use – Compliant with standard P&R and floorplanning (minimum inter-channel routing constraints) – Robustness CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 11
Crosstalk • Substrate crosstalk an issue in CMOS (no deep trenches) – SOI would solve this issue • Differential topologies minimize supply crosstalk • Magnetic coupling through inductors? CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 12
Synchronicity / Plesiochronicity D 0 D 1 D 2 faster (f B + ∆ f) D 3 D 4 D 5 D 6 D a+ D 7 D a- D 8 D b+ D 9 D b- D 10 D 11 D 12 D 13 slower (f B - ∆ f) D 14 D 15 16-bit synchronous parallel bus 2-channel serial link CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 13
Eye Diagram A unit interval (UI) is equal to an average bit period CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 14
Jitter and Probability Density Functions • Random jitter (RJ) – Has a Gaussian distribution – Amplitude measured in UIRMS • Deterministic jitter (DJ) – Considered uniform – Amplitude measured in UIPP • Sinusoidal jitter (SJ) – Sine-wave phase modulation – Amplitude measured in UIPP CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 15
Jitter Tolerance (JTOL) [InfiniBand TM Specification] – Data Rate 2.5Gb/s CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 16
Data Encoding • 8b/10b data encoding • Loss of bandwidth (20%), e.g. InfiniBand™: – Signal rate 2.5 GBd – Effective data rate 2.0 Gb/s • Transition density = 0.6 • DC balance • Limited low-frequency spectral content • Maximum run length of 5 bits (K28.5 pattern) …00111110101100000101… CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 17
Outline • Motivation • Particularities of Short-Distance Links • Pure Silicon Photodetectors • Transimpedance and Limiting Amplifier Design • Gated Oscillator CDR • Conclusion CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 18
Resonant Cavity Enhancement Bandwidth-efficiency Incident light tradeoff in standard silicon PIN photodetectors ⇒ insufficient efficiency at high data rates ⇒ implementation of a resonant cavity to increase the light path distance in the absorption region CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 19
Resonant Cavity Enhancement A Fabry-Perrot cavity using two Bragg reflectors is built into the silicon photodetector Photodetector p + contact Window n + contact upper mirror ( Si − Air interface) Incident p + region light Si n+ contact n + region implant SiO 2 Si lower mirror SiO 2 Silicon Substrate CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 20
Silicon-Only Photodetector The integrated resonant cavity improves the detector efficiency dramatically CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 21
12x1 Photodiode Array CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 22
Outline • Motivation • Particularities of Short-Distance Links • Pure Silicon Photodetectors • Transimpedance and Limiting Amplifier Design • Gated Oscillator CDR • Conclusion CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 23
Gain-Bandwidth Tradeoff • Limiting amplifier performance determined by the achievable gain-bandwidth product target: BW tot = 4.5GHz A v0 = 29dB • Optimum gain per stage for cascaded topologies ≅ 2 [T. H. Lee] but BW tot < 2GHz • Available trade-off improvements – Increased supply voltage ⇒ reliability issues – Cherry-Hooper topology ⇒ suffers of shrinking supplies – Active inductors ⇒ require high gate voltage – Spiral inductors ⇒ silicon area (?), design parameters (?) – Inter-stage downscaling ⇒ Comparative Study of Inductorless and Inductive Peaking Topologies CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 24
Inductorless Limiting Amplifier For 1 st -order stages with identical gain and cut- off frequency: N = ∏ N = Av Av Av DC DCi DCi i = 1 BW = f ⋅ 2 − 1 N ci CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 25
Amplifier Optimization (1/3) N g 1 = ⋅ ⋅ ⋅ − Av h 2 1 mu N ( ) DC 2 π ⋅ BW C ⋅ 1 + α ⋅ h W CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 26
Amplifier Optimization (2/3) Considered C W Solution = = h N in in C W load load CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 27
Amplifier Optimization (3/3) Considered Solution P N ∑ = h n − 1 tot P n = 1 0 CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 28
Inductive Peaking Amplifier • Same cascaded amplifier topology, but no inter-stage scaling • Inductors need a lot of silicon area Lower bias currents ⇒ reduced device area • Absence of reliable model parameters ⇒ conservative design • High Q-factor is not needed ⇒ further area reduction possible • • Risk of magnetic coupling? 3 1 2 CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 29
Simulated Transfer Function Av LA [dB] without L 30 20 with L 10 0 1M 100M 10G f [Hz] -10 -20 -30 CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 30
Amplifier Layouts 840µm 470µm 1160µm Inductorless Amplifier 440µm Inductive Peaking Amplifier CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 31
Inductorless LA Results 22mV 400ps 1UI = 400ps CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 32
Inductive Peaking LA Results 221mV 400ps CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 33
Coupling Measurements 100mV Channel 1 Input 20mV Channel 2 Output CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 34
Summary of Results Simulation Measurement Amplifier Type w/o L with L w/o L with L min max min max min max min max Technology 0.18µm Digital CMOS Supply Voltage [V] 1.62 1.98 1.62 1.98 1.6 2 1.6 2.0 Bandwidth [GHz] 3.7 4.5 1.5 1 Voltage Gain [dB] 25 23 4? 20 Input Ref. Noise @1GHz 0.6 2.3 30.5? 11.0 [nV/ √ Hz] I VDD [mA] @ 25 ° C 60 7.5 20 6.4 Area [mm 2 ] 0.40 0.51 - - CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 35
Transimpedance Amplifier CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 36
Simulated Transimpedance Gain Z TIA [dB Ω ] 80 40 0 1 E 6 1 E 8 1 E 10 f [Hz] CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 37
Measured “Eye” Diagram C IN ≈ 0.2pF f b =2.5Gb/s 25mV Simulated with C IN =0.8pF 400ps CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 38
Die Microphotograph 530µm TIAs C C C C H H H H LAs A A A A 470µm N N N N N N N N E E E E L L L L Bias 1 2 3 4 50 Ω Drivers CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 39
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