A fA-Range Low-Power Multi-Channel Digital A fA-Range Low-Power - PowerPoint PPT Presentation

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 1/30 A fA-Range Low-Power Multi-Channel Digital A fA-Range Low-Power Multi-Channel Digital Read-Out Integrated Circuit for Differential Read-Out Integrated Circuit for Differential Mobility Analyzers Mobility Analyzers A. Jemni, F. Serra-Graells and L. Teres Teres aymen.jemni@imb-cnm.csic.es y j Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona. IMB-CNM(CSIC) ( ) November 2010 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 2/30 Introduction 1 ROIC Channel Architecture O C Ch l hi 2 2 Reset times 3 4 Switch Leakage CMOS Integration and Simulation Results 5 6 T 6 Test Environment t E i t Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 3/30 Introduction 1 ROIC Channel Architecture 2 Dead times Dead times 3 3 4 Switch Leakage CMOS Integration and Simulation Results 5 6 Test Environment Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 4/30 Introduction Introduction Aerosol identification for  medicine, biology, environment di i bi l i t monitoring, security… Differential Mobility Analyzer Differential Mobility Analyzer   (DMA): ion/particle classification according to mass and charge  L  Long acquisition time (several i iti ti ( l seconds) A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 5/30 Introduction Introduction Aerosol identification for  medicine, biology, environment di i bi l i t monitoring, security… Differential Mobility Analyzer Differential Mobility Analyzer   (DMA): ion/particle classification according to mass and charge  Long acquisition time (several  L i iti ti ( l seconds) Array of independent and Array of independent and   separated microelectrodes Parallel signal processing  Fast acquisition time (ms) for the  same noise bandwidth A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 6/30 1 Introduction ROIC Channel Architecture 2 Dead times Dead times 3 3 4 Switch Leakage CMOS Integration and Simulation Results 5 6 Test Environment Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 7/30 ROIC Channel Architecture ROIC Channel Architecture Param eter Value Units Main specifications of Main specifications of   the ROIC Channel pitch 50 µm Micro-electrode resistance ≤ 50 Ω Compact channel area  Micro-electrode capacitance ≤ 2 pF Short acquisition time  Acquisition time 1 : 100 ms High current sensitivity High current sensitivity   I Input resolution (@100ms) t l ti (@100 ) ±1 ±1 fA fA Input dynamic range 80 dB Wide dynamic range  Supply voltage Supply voltage 3 3 3.3 V V L Low-power operation ti   Power consumption < 0.5 mW/Ch Temperature (@100ms) -20:0:30 ºC A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 8/30 ROIC Channel Architecture ROIC Channel Architecture Integrating A/D  Conversion  Full-parallel signal processing.  No input signal  N i t i l multiplexing is required.  Narrow noise  Narrow noise bandwidth.  Minimum crosstalk.  Fixed pattern noise compensation.  Low power CMOS and compact circuits required. q A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 9/30 1 Introduction ROIC Channel Architecture 2 Reset times Reset times 3 3 4 Switch Leakage CMOS Integration and Simulation Results 5 6 Test Environment Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 10/30 Reset Times Reset Times Novel integration scheme for Novel integration scheme for   in-channel ADC conversion.  High linearity.  Correlated Double Sampling (CDS).  Compact CMOS circuits. A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 11/30 Reset Times Reset Times Novel PDM scheme for f   minimum reset time during integration:  High linearity.  Correlated double sampling (CDS). li (CDS)  Robust.  Compact CMOS circuits. A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 12/30 1 Introduction ROIC Channel Architecture 2 Dead times Dead times 3 3 Switch Leakage 4 CMOS Integration and Simulation Results 5 6 Test Environment Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 13/30 Switch Leakage Switch Leakage MOSFET switch non-idealities:   Subthreshold conduction  D/S diffusion diodes leakage A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 14/30 Switch Leakage Switch Leakage MOSFET switch non-idealities:  Proper n-well  biasing ( V biasing ( V bulk ) ) I leak ≤ 0.5 fA  A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 15/30 1 Introduction ROIC Channel Architecture 2 Dead times Dead times 3 3 Switch Leakage 4 CMOS Integration and Simulation Results 5 6 Test Environment Conclusions 7 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 16/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Full channel layout in 0.35 µm 2P4M CMOS technology:  A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 17/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results CMOS noise dominate CMOS noise dominate   over electrode noise 65% thermal and 35%  fli k flicker Adequate LSB for 1 fA  resolution A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 18/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results PDM transfer function PDM transfer function    Poor linearity at full- scale A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 19/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Local bias generator Local bias generator    Flat temperature sensitivity A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 20/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Parameter Value Units Main performance  Channel pitch 50 µm parameters of the ROIC t f th ROIC Silicon area mm 2 0.12 channel module Acquisition time 1 : 100 ms Equivalent input noise (@100ms) q p ( ) 0.4 fA rms rms Instantaneous dynamic range 84 dB Overall dynamic range 100 dB Threshold range ( V Threshold range ( V th ) ) ±250 : ±650 ±250 : ±650 mV mV Threshold step ( ∆ V th ) ±10 mV Supply voltage 3.3 V Current consumption 110 µA A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 21/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results First test vehicle prototype: First test vehicle prototype:    1 pre-amp block  1 PDM bl  1 PDM block k  10 operative channels with external programming external programming  20 full channels with serial interface 035um CMOS 2P 4M technology  (AMS-C35) Bump bonding  2950µm x 2850µm = 8.4mm 2 A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 22/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Second version with enhanced performance and compact layout:  A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 23/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results  High Linearity of the PDM  High Linearity of the PDM  High sensitivity (20Hz/fA) A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 24/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Main performance  parameters of the ROIC Param eter Value Units channel module Channel pitch Ch l h 45 µm Silicon area mm 2 0.054 Acquisition time 1 : 100 ms Equivalent input noise (@100ms) 0.4 fA rms Instantaneous dynamic range 120 dB Overall dynamic range 100 dB Threshold range ( V th ) ±50 : ±650 mV Threshold step ( ∆ V th ) ±10 mV Supply voltage pp y g 3.3 V Current consumption 110 µA A. Jemni et al. IMB-CNM(CSIC)

DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 25/30 CMOS Integration and Simulation Results CMOS Integration and Simulation Results Second test vehicle prototype: Second test vehicle prototype:    1 pre-amp block  1 PDM bl  1 PDM block k  1 operative channel with external programming external programming  2 full channels with serial interface 035um CMOS 2P 4M technology  (AMS-C35) 2000µm x 1300µm = 2.6mm 2 Wire bonding  A. Jemni et al. IMB-CNM(CSIC)