Slides for Lecture 6 ENEL 353: Digital Circuits Fall 2013 Term - PowerPoint PPT Presentation

Slides for Lecture 6 ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 20 September, 2013

slide 2/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Previous Lecture ◮ ranges for two’s-complement systems ◮ overflow in two’s-complement addition ◮ BCD (binary coded decimal) codes for decimal digits ◮ Gray codes

slide 3/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Today’s Lecture A little more about Gray codes. Introduction to logic gates. Related reading in Harris & Harris: Section 1.5

slide 4/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Gray code to unsigned binary code conversion, unsigned binary code to Gray code conversion n -bit Gray code ... 0 ... extra 0 not part n -bit binary code of either code The Gray code bit is 0 if the adjacent binary code bits match each other. Otherwise the Gray code bit is 1. Let’s convert 4-bit binary 0110 to Gray code, and 6-bit Gray code 101110 to binary.

A 4-bit shaft encoder : Optical sensors make a digital measurement of the rotation angle of a spinning metal disk. This could be used for a digital weathervane, indicating one of 16 wind directions N, NNE, NE, ENE, . . . , NNW. This version uses unsigned binary encoding for positions 0 to 15. Why is this encoding a poor design choice?

slide 6/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Practical shaft encoders use Gray codes If the light and dark markings on the spinning disk are organized using a Gray code, that eliminates the problem of having two or more bits change at almost but not exactly the same time. Very precise shaft encoders can measure very small changes in angles in industrial equipment. For example, a 12-bit shaft encoder measures rotation angle to within 360 ◦ / 2 12 = 0 . 088 ◦ .

slide 7/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Combinational versus Sequential Logic It’s IMPORTANT to know what these words mean. The outputs of a combinational logic circuit depend only the current values of its inputs. The outputs of a sequential logic circuit depend on the history of its input values.

slide 8/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Example combinational circuit: 1-bit full adder A B C in The values of C out and S depend on what the values of A , B , and C in are full RIGHT NOW, not what they were a adder few minutes ago, or even a few nanoseconds ago. C out S

slide 9/21 ENEL 353 F13 Section 02 Slides for Lecture 6 What does the term logic gate mean? A logic gate is a combinational logic circuit that has ◮ one or more inputs , each of which is a bit ; ◮ exactly one output , which is a bit . According to this definition, is the full adder a logic gate?

slide 10/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Graphical and algebraic notations for some common 1- and 2-input logic gates A Y = A A Y = A ⊕ B B A Y = A A Y = AB B A Y = AB A B Y = A + B B A Y = A + B A B Y = A ⊕ B B We’ll now examine these gates one or two at a time . . .

slide 11/21 ENEL 353 F13 Section 02 Slides for Lecture 6 1-input gates A NOT gate, also called an inverter : A Y = A In A is the input and Y is the output. The “bubble” in the symbol indicates inversion: 0 converted to 1, and 1 converted to 0. The equation Y = A is read, “Y equals NOT A.” A buffer : A Y = A The output Y is just a copy of the input A . Logically this is no different from a wire, but electrically, a buffer can help with circuit timing, making sure a device gets enough input current, and so on.

slide 12/21 ENEL 353 F13 Section 02 Slides for Lecture 6 An alternate notation for the NOT operation The “overline” is probably the most common notation for the NOT operation, but there is another symbol in wide use. Many textbooks and other documents use the ′ symbol (“prime”) instead. This includes the textbook used last year in ENEL 353. This year we will use an “overline” for the NOT operation, to be consistent with this year’s textbook. If you see A ′ in course material from past years, translate that in your head to A .

slide 13/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Truth tables A truth table describes a combinational logic element by making a list of the values of the output for all possible combinations of input bits. (We’ve already seen the truth table for the 1-bit full adder.) Let’s write out the very simple truth tables for a NOT gate and a buffer.

slide 14/21 ENEL 353 F13 Section 02 Slides for Lecture 6 When writing in English about logic gates, use ALL CAPS for the names of gates Confusing: “For this design you may use or or and gates but not not gates.” Better: “For this design you may use OR or AND gates but not NOT gates.”

slide 15/21 ENEL 353 F13 Section 02 Slides for Lecture 6 The AND gate Here is the symbol and the algebraic notation: A Y = AB B One way to remember the symbol is to remember that the word AND contains a D, and the symbol looks like a D. An alternate algebraic notation for AND uses the · symbol, as in Y = A · B . Here is how the AND operation is defined: � 1 if both A and B are 1 AB = 0 otherwise Let’s write the truth table for AND .

slide 16/21 ENEL 353 F13 Section 02 Slides for Lecture 6 The OR gate Symbol and algebraic notation . . . A Y = A + B B Here is how the OR operation is defined: � 0 if both A and B are 0 A + B = 1 otherwise In other words, in digital logic, OR means “one or the other or both are true.” Let’s write the truth table for OR .

slide 17/21 ENEL 353 F13 Section 02 Slides for Lecture 6 In discussion of digital logic, + does not mean arithmetic addition ◮ In decimal arithmetic, what is 1 + 1 ? ◮ In binary arithmetic, what is 1 + 1 ? ◮ In digital logic, what is 1 + 1 ? This can be confusing, especially when discussing digital logic circuits that are designed to do arithmetic!

slide 18/21 ENEL 353 F13 Section 02 Slides for Lecture 6 The XOR gate XOR is short for exclusive OR . A Y = A ⊕ B B “Exclusive or” means “one or the other but not both .” � 1 if one of A and B is 1 and the other is 0 A ⊕ B = 0 otherwise Let’s write the truth table for XOR .

slide 19/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Convention for ordering of truth table input combinations ◮ Start with the row for all inputs = 0. ◮ Alternate 0’s and 1’s most slowly on the left. ◮ Alternate 0’s and 1’s more quickly as you move left to right. ◮ Alternate 0’s and 1’s most quickly—every row—on the right. ◮ In other words, write the input bit patterns in unsigned binary ordering.

slide 20/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Convention for ordering of truth table input combinations: Examples This follows the These two tables convey the same information, but should be AVOIDED! convention . . . A B C Y A B C Y A B C Y 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1

slide 21/21 ENEL 353 F13 Section 02 Slides for Lecture 6 Next Lecture More 2-input gates: NAND, NOR and XNOR. Examples of gates with 3 or more inputs. Correspondences between bit values and voltage levels in digital circuits. Related reading in Harris & Harris: Sections 1.5 and 1.6.