Slides for Lecture 33 ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 27 November, 2013
slide 2/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Previous Lecture Completion of a timing analysis example. Introduction to clock skew . Adjustment of setup and hold time constraint inequalities to account for clock skew. What can happen when setup and hold time constraints are violated? Introduction to metastability .
slide 3/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Today’s Lecture The problem of asynchronous inputs to synchronous systems; solution with synchronizer circuits. Some insight into where metastability and setup times come from. Related reading in Harris & Harris: Sections 3.4.4–3.4.5.
slide 4/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Preventing metastability from causing circuit failure A single DFF going metastable for a fraction of a clock cycle may cause a synchronous system to behave incorrectly for a much longer time period, and may even cause the system to freeze completely. One essential step in CLK reducing the risk of problems is, as we’ve just C seen, careful timing analysis L of paths like this . . . But what about system inputs? Edges on inputs can have completely unpredictable timing relative to edges on the the system clock!
slide 5/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Examples of asynchronous inputs In each of the systems below, A is what is called an asynchronous input . . . CLK1 CLK2 CLK button synchro- synchro- A nous nous A synchronous system 1 system 2 system CLK1 and CLK2 are unrelated , with different frequencies. On the left, the system can’t control when a human might press or release the button. On the right, there will be no predictable relationship between edges on A and edges on CLK2.
slide 6/23 ENEL 353 F13 Section 02 Slides for Lecture 33 An example FSM with an asynchronous input If we don’t know anything at all about when edges on A might appear relative to edges on CLK, this is a bad design . . . CLK next A output state Y logic logic Why is it impossible to design the next state logic to prevent disastrous metastability in the state register? To greatly reduce the risk, A can be passed though a synchronizer circuit , as shown on the next slide . . .
slide 7/23 CLK n1 n2 next A output state Y logic logic FF1 FF2 synchronizer circuit Suppose the next state logic has been designed so that its t pd and t cd meet setup and hold constraints for the state register. Recall that t res is the resolution time for a DFF or register. Suppose that a detailed transistor-level model says that it is extremely unlikely that it will ever happen that t res > 0 . 5 T C . Let’s give an approximate, qualitative argument that there is very little risk of metastability in the state register.
slide 8/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Detailed analysis of t res and synchronizers In Sections 3.4.4–3.4.6, Harris and Harris present a formula for the probability distribution of t res : P ( t res > t ) = T 0 � − t � exp τ T C They go on to use that probability distribution to derive a formula for MTBF (mean time between failures) of synchronizer circuits. In ENEL 353 in Fall 2013, we are not going to cover that material, and you will not be tested on it on the final exam. You are expected to understand the qualitative ideas about metastability and synchronizers presented in Sections 3.4.4 and 3.4.5.
slide 9/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Some insight into circuits, setup times, and metastability The rest of the slides in this lecture are not exam material in ENEL 353 in Fall 2013. They are intended to provide some insight into why latches and flip-flops must have setup times, and why latches and flip-flops can go metastable.
slide 10/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Static behaviour of CMOS NOT, NOR, and NAND gates If we slowly vary the voltage at A in each of the circuits below, and measure the voltage at Y as we go, we’ll see an input/output relationship that looks something like the graph sketched to the right. A Y V DD voltage at Y A Y 0 0 V DD Y voltage at A A
slide 11/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Static solutions for some bistable circuits gate 1 For each of the circuits, there are Q three static conditions that satisfy QN input/output voltage relationships for gate 2 both gates . . . gate 1 0 Q V DD voltage at QN gate 2 QN 0 gate 2 gate 1 gate 1 1 Q 0 0 V DD QN voltage at Q 1 gate 2
slide 12/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Static solutions for bistable circuits, continued The upper-left and lower-right solutions are the V DD voltage at QN stable solutions predicted gate 2 by Boolean algebra: (Q , QN) = (0 , 1) and (Q , QN) = (1 , 0). gate 1 Boolean algebra only works 0 with 1’s and 0’s, so cannot 0 V DD predict the metastable voltage at Q solution in the middle of the graph.
slide 13/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Dynamic behaviour of bistable circuits Static analysis shows us only what the possible solutions are when dV / dt = 0 for both gate outputs, and does not tell us how voltages might change as a function of time. Transistor physics and circuit theory, beyond what has been taught to year 2 ENEL and ENSF students, says . . . ◮ The static solutions that are identified by Boolean algebra are stable equilibrium points . If a bistable circuit is in one of its stable states, moderate amounts of electrical noise will not move the state very far away from that stable state. ◮ The metastable state of a bistable circuit is an unstable equilibrium point . A very tiny amount of electrical noise will rapidly drive the circuit from there into one or the other of its stable states.
slide 14/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Metastability in a D flip-flop We studied this design in lectures and also in Lab 4. It’s not how D flip-flops are constructed in most modern integrated circuits, but the design is relatively easy to understand. master D latch slave D latch D R M Q M Q FF QN M S M CLK Reminder: Because CLK passes through a NOT gate before entering the master latch, the master latch is transparent when CLK is LOW.
slide 15/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Let’s look at what happens in the master latch when there is an edge on D just before a rising edge on CLK. D R M CLK Q M D R M QN M S M S M CLK In an ideal SR latch, (Q M , QN M ) will go to (1 , 0) because of the pulse on S M . But in a real SR latch, the width of the pulse matters. A wide pulse will make the latch “do the right thing.” A very narrow pulse will not decrease the voltage at QN M very much, and the voltage at Q M won’t change at all. (Q M , QN M ) will settle back to (0 , 1).
slide 16/23 ENEL 353 F13 Section 02 Slides for Lecture 33 D R M CLK Q M D R M QN M S M S M CLK If the width of the pulse on S M is “perfectly wrong” the voltages at Q M and QN M will both be near 0 . 5 V DD when the pulse ends. That gives the pair of NOR gates a chance to go metastable!
slide 17/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Now let’s have another look at the slave latch . . . master D latch slave D latch D R M Q M Q FF QN M S M CLK When CLK is HIGH, the slave latch is supposed to be transparent. But if Q M ≈ 0 . 5 V DD , both AND gates in the slave have “forbidden zone” inputs, and we cannot rely on Q FF to have any particular value. If it’s still true that Q M ≈ 0 . 5 V DD when CLK goes from HIGH to LOW, that could make the NOR gates in the slave go metastable.
slide 18/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Setup time in a modern DFF Below is a D latch suitable for use as the master latch in a DFF. Switches S1 and S2 are implemented in CMOS using simple two-transistor devices called transmission gates . S1 I1 I2 Q M n1 D S2 QN M I3 CLK CLK CLK CLK CLK S1 S2 latch condition LOW closed open transparent HIGH open closed opaque
slide 19/23 ENEL 353 F13 Section 02 Slides for Lecture 33 S1 I1 I2 Q M n1 D S2 QN M I3 CLK CLK CLK CLK When CLK is LOW, S1 is closed and S2 is open. I1 and I2 form a simple buffer. When CLK is HIGH, S1 is open and S2 is closed. I2 and I3 form a bistable circuit that can lock the state in either (Q M , QN M ) = (0 , 1) or (Q M , QN M ) = (1 , 0).
slide 20/23 ENEL 353 F13 Section 02 Slides for Lecture 33 S1 I1 I2 Q M n1 D S2 QN M I3 CLK CLK CLK CLK What happens if there is an edge on D, just before a rising edge on CLK that will break the connection though S1? I1 may not have enough time to drive node n1 to the correct voltage for D, with one of two possible bad outcomes: ◮ Q M could fail to copy the new value of D. ◮ If the n1 voltage is “just wrong”, the bistable circuit made from I2 and I3 could go metastable. If the signal at D respects a setup time specification, then the above bad outcomes can’t happen.
slide 21/23 ENEL 353 F13 Section 02 Slides for Lecture 33 Some connections to the textbook and other literature , not , is the usual symbol for a transmission gate. CLK CLK A B A B CLK CLK On the left, A and B are connected when CLK is HIGH. On the right, A and B are connected when CLK is LOW.
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