Slides for Lecture 22 ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 30 October, 2013
slide 2/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Previous Lecture Critical paths and short paths, finding overall t pd and t cd . Examples of overall t pd and t cd calculations. Example of a glitch.
slide 3/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Today’s Lecture Completion of discussion of glitches. Introduction to sequential logic. The SR latch. Related reading in Harris & Harris: Sections 2.9.2, 3.1, 3.2 (material before 3.2.1), 3.2.1.
slide 4/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Glitches (repeat slide from previous lecture) A n2 C Y n1 B n3 What is Y when ( A , B , C ) = (1 , 1 , 1) ? What about ( A , B , C ) = (1 , 1 , 0) ? Suppose the delays are 30 ps for NOT, 50 ps for AND, and 60 ps for OR. Let’s make a timing diagram to show what happens to Y when ( A , B , C ) goes from (1 , 1 , 1) to (1 , 1 , 0) .
slide 5/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Timing diagram for glitch example 1 A 0 1 B 0 1 C 0 1 n1 0 1 n2 0 1 n3 0 1 Y 0 t =0ps 30ps 50ps 80ps 110ps 140ps Let’s write down a few remarks about this diagram.
slide 6/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Are glitches bad? In certain specialized digital design problems, avoidance of glitches in combinational outputs is very important. Usually, though, glitches are not a concern, and what really matters in timing of combinational logic is making sure that overall propagation delay is not long. (Sometimes low power consumption is even more important than small propagation delay.) In Section 2.9.2, Harris & Harris present a method based on K-maps that can sometimes be used to make circuits glitch-free. We’re not going to study that in ENEL 353.
slide 7/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Combinational versus Sequential Logic This is review: The outputs of a combinational logic circuit depend only the current values of its inputs. The outputs of a sequential logic circuit depend on the history of its input values. We’ve just seen that the above definition of combinational logic is very slightly untrue, due to very tiny delays. However, sequential logic is totally different . Outputs may depend on the history of input values indefinitely far back in the past —minutes, hours, or days, not just picoseconds.
slide 8/13 ENEL 353 F13 Section 02 Slides for Lecture 22 SR latches Here are two ways to build an SR latch, perhaps the simplest sequential circuit element: NAND-based NOR-based S R Q Q QN QN R S Notice that it’s possible to wire together combinational devices in ways that produce sequential devices! Harris & Harris use Q and Q as names of outputs, but I prefer Q and QN because—as we’ll soon see—it’s not always true that QN = NOT(Q).
slide 9/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Static analysis of the SR latch We’ll look at the NOR-based circuit. (Analysis of the NAND-based circuit is very similar.) Q = ( R + QN) R QN = ( S + Q) Q Q depends on QN, and QN depends on Q. QN S This is a system of two Boolean algebra equations in two unknowns! For all four possible combinations of R and S, let’s solve for Q and QN.
slide 10/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Dynamic behaviour of a NOR-based SR latch useful problematic behaviour behaviour 1 S 0 1 R 0 1 Q ? ? ? ? 0 1 QN ? ? ? ? 0 A pulse on S or R is a transition from 0 to 1, followed later by a transition from 1 to 0. Let’s make some notes about useful and problematic behaviour of the SR latch.
slide 11/13 ENEL 353 F13 Section 02 Slides for Lecture 22 The SR latch is an example of a bistable circuit A bistable circuit is one that will sit in either one of two stable states. We’ve just seen that an SR latch is bistable when S = R = 0: either (Q , QN) = (0 , 1) or (Q , QN) = (1 , 0). It’s important to understand that if there are no pulses on S or R , the state of an SR latch will persist as long as the circuit is powered up. When S = R = 0, the state will not spontaneously flip between (Q , QN) = (0 , 1) and (Q , QN) = (1 , 0). (Unless the latch is affected by severe electrical noise.) To understand why the state is stable when S = R = 0, you need to study the pull-up and pull-down networks of the gates that make up an SR latch. That is not an ENEL 353 topic.
slide 12/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Symbols for SR latches It’s less important to know what is going on inside an SR latch (NOR gates, NAND gates, inverters and/or other devices) than it is to know its behaviour as a “black box”. ( Black box: You can play with its inputs and observe its outputs, but you can’t look inside it.) Here are two symbols, one from our course textbook, and another from an author named Wakerly . . . S Q S Q R Q R QN (Wakerly’s Digital Design book is very good, but for a beginner, reading it may be somewhat like trying to drink from a firehose.)
slide 13/13 ENEL 353 F13 Section 02 Slides for Lecture 22 Upcoming topics Introduction to sequential logic. D latches and D flip-flops. Related reading in Harris & Harris: Sections 3.2.2–3.2.6.
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