Slides for Lecture 18 ENCM 501: Principles of Computer Architecture Winter 2014 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 18 March, 2014
slide 2/8 ENCM 501 W14 Slides for Lecture 18 Previous Lecture ◮ review of floating-numbers and operations ◮ effects of multiple-cycle EX-stage computation ◮ in-order versus out-of-order execution ◮ WAW and WAR data hazards
slide 3/8 ENCM 501 W14 Slides for Lecture 18 Today’s Lecture ◮ WHAT Related reading in Hennessy & Patterson: Sections WHAT
slide 4/8 ENCM 501 W14 Slides for Lecture 18 Review: A slide from the previous lecture Integer unit EX FP/integer multiply M1 M2 M3 M4 M5 M6 M7 IF ID MEM WB FP adder A1 A2 A3 A4 FP/integer divider DIV Image is Figure C.35 from Hennessy J. L. and Patterson D. A., Computer Architecture: A Quantitative Approach, 5nd ed. , c � 2012, Elsevier, Inc.
slide 5/8 ENCM 501 W14 Slides for Lecture 18 More problems related to long latency The divide unit in the Figure C.35 computer has a 24-cycle latency and is not pipelined . What kind of hazard is created by the lack of pipelining in the divide unit? What is the effect of the 4-cycle FP add latency and the 7-cycle multiply latency on the frequency and severity of RAW data hazards? (In other words, how bad are the RAW hazards, relative to how bad they could be in the simple 5-stage system that supports only LW, SW, BEQ, and some integer R-type instructions?)
slide 6/8 ENCM 501 W14 Slides for Lecture 18 Review: Practical WAW hazard, and a WAR hazard MUL.D F2, F4, F6 S.D F2, 0(R8) some hazard-free instructions L.D F2, 0(R9) ADD.D F8, F8, F2 With out-of-order (OOO) issue, L.D could complete before MUL.D, and S.D could then read the wrong value from F2—that’s an example of a WAR hazard. With OOO issue, MUL.D could write to F2 after L.D writes to F2, causing ADD.D and later instructions to use the wrong value of F2—that’s an example of a WAW hazard.
slide 7/8 ENCM 501 W14 Slides for Lecture 18 Name dependencies The problems in the example of the previous slide stem from the decision to use F2 for two different and unrelated intermediate results. It would be safe to start L.D and ADD.D before S.D if some other register were used for the result of L.D . . . MUL.D F2, F4, F6 S.D F2, 0(R8) some hazard-free instructions L.D F10, 0(R9) ADD.D F8, F8, F10
slide 8/8 ENCM 501 W14 Slides for Lecture 18 Upcoming Topics ◮ Processing instructions with parallel pipelines. Related reading in Hennessy & Patterson: Sections 3.1, 3.4, 3.5
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