Lecture 1: Introduction to Digital Logic Design CK Cheng CSE Dept. - PowerPoint PPT Presentation

Lecture 1: Introduction to Digital Logic Design CK Cheng CSE Dept. UC San Diego 1

Outlines • Administration • Motivation • Scope 2

Administration Web site: http://www.cse.ucsd.edu/classes/fa12/cse140-a/ WebCT: http://ted.ucsd.edu 3

Administration Instructor: CK Cheng, CSE2130, ckcheng+140@ucsd.edu, 858 534-6184 Teaching Assistants: • Shih-Hung Weng, s2weng@ucsd.edu • Jyoti Wadhwani, jwadhwan@ucsd.edu 4

Administration Schedule • Outline (Use index to check the location of the textbooks) • Lectures: 3:00-3:50PM, MWF, Center 115. • Discussion: 9:00-9:50AM, F, Center 101. • Office hours: CSE2130 – 10:30-11:30AM, T – 1:00-2:00PM, W 5

Administration Textbook: Digital Design and Computer Architecture, D.M. Harris and S.L. Harris, Morgan Kaufmann, Second Edition, 2012. Grading • iClicker: 5% (a ramp function saturates at 80% of class points) • CK Cheng Office Hr. visits: 2% bonus (1% per visit) • Homework: 10% (grade on style, completeness or correctness) • Midterm 1: 25% (M 10/22) (style, completeness and correctness) • Midterm 2: 30% (W 11/14) • Midterm 3: 30% (F 12/07) • Optional take home final exam due 6PM, F. 12/14: 1% bonus 6

Motivation • Microelectronic technologies have revolutionized our world: cell phones, internet, rapid advances in medicine, etc. • The semiconductor industry has grown from $21 billion in 1985 to $304 billion in 2010. 7

Robert Noyce, 1927 - 1990 • Nicknamed “Mayor of Silicon Valley” • Cofounded Fairchild Semiconductor in 1957 • Cofounded Intel in 1968 • Co-invented the integrated circuit 8

Gordon Moore, 1929 - • Cofounded Intel in 1968 with Robert Noyce. • Moore’s Law: the number of transistors on a computer chip doubles every year (observed in 1965) • Since 1975, transistor counts have doubled every two years. 9

Moore’s Law “If the automobile had followed the same development cycle as the computer, a Rolls-Royce would today cost $100, get one million miles to the gallon, and explode once a year . . .” – Robert Cringley 10

iClicker • The purpose of this course is that we: A. Learn what’s under the hood of an electronic component B. Learn the principles of digital design C. Learn to systematically debug increasingly complex designs D. Design and build digital systems E. All of the above F. Most of the above 11

iClicker Digital system can be built upon A. Mechanical relays B. Silicon transistors C. DNAs D. Quantum mechanical phenomena E. All of the above 12

Scope: Position in the Design Flow The class assumes Application programs Software CMOS transistors Operating device drivers Systems AND, OR logic instructions Architecture registers focus of this course Micro- datapaths architecture controllers Flip-Flip registers adders Logic memories Synchronous designs, Digital AND gates Circuits NOT gates Analog amplifiers but the application Circuits filters transistors Devices reaches beyond the diodes Physics electrons assumed region. 13

Scope: Sequence of Courses • CSE20: Discrete Math • CSE140/L: Digital System • CSE141/L: Computer Architecture • CSE142-149: Architecture, Design Automation, Embedded Systems • CSE237, 240-249, 291: Architecture, Design Automation, Embedded Systems • ECE260A-C: VLSI Designs 14

Scope: Content We will cover four major things in this course: - Combinational Logic (H2) - Sequential Networks (H3) - Standard Modules (H5) - System Design (H4, H6-8) 15

Scope: Overall Picture of CS140 Data Path Subsystem Input Memory File Conditions Pointer Mux Control Subsystem ALU Control Memory Register Conditions CLK: Synchronizing Clock 16

Combinational Logic vs Sequential Network x 1 x 1 x 1 . . . . f i (x) f i (x) . . f i (x) f i (x) f i (x) f i (x) s i . . . x n x n x n CLK Sequential Networks Combinational logic: 1. Memory 2. Time Steps (Clock) y i = f i (x 1 ,..,x n ) t = f i (x 1 t ,…,x n t , s 1 t , …,s m t ) y i t+1 = g i (x 1 t ,…,x n t , s 1 t ,…,s m t ) s i 17

Scope Subjects Building Blocks Theory Combinational AND, OR, Boolean Algebra Logic NOT, XOR Sequential AND, OR, Finite State Network NOT, FF Machine Standard Operators, Arithmetic, Modules Universal Logic Interconnects, Memory System Design Data Paths, Methodologies Control Paths 18

Perspective Class notes Homework Textbook 19

Part I. Combinational Logic ab a ab + cd b e (ab+cd) c d cd e • I) Specification • II) Implementation • III) Different Types of Gates 20