I I I -Vs for CMOS Beyond Silicon J. A. del Alamo Microsystems - PowerPoint PPT Presentation

I I I -Vs for CMOS Beyond Silicon J. A. del Alamo Microsystems Technology Laboratories, MIT MIT Lincoln Laboratory Advanced Research and Technology Symposium February 26-27, 2013 Acknowledgements: • D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia • Sponsors: Intel, FCRP-MSD • Labs at MIT: MTL, NSL, SEBL 1

I I I -V HEMT Electronics Today UMTS-LTE PA module Chow, MTT-S 2008 40 Gb/s modulator driver 77 GHz transceiver Carroll, MTT-S 2002 Tessmann, GaAs IC 1999 Bipolar/E-D PHEMT process Single-chip WLAN MMIC, Morkner, RFIC 2007 Henderson, Mantech 2007 2

I I I -V HEMT: record f T vs. time Current record: f T =688 GHz f max =800 GHz Kim IEDM 2011 (Teledyne/MIT) Devices fabricated at MIT • For >20 years, record f T obtained on InGaAs-channel HEMTs • InGaAs-channel HEMTs offer record balanced f T and f max 3

I nAlAs/ I nGaAs HEMTs at MI T Gate S D Oxide Cap - QW channel (t ch = 10 nm): Etch stopper • InAs core Barrier t ins • InGaAs cladding t ch Channel   n,Hall = 13,200 cm 2 /V-sec Buffer - InAlAs barrier (t ins = 4 nm) - L g =30 nm Kim, EDL 2010 4 4

L g = 30 nm I nGaAs HEMT V GS = 0.8 0.4 V Kim, EDL 2010 0.6 I D [mA/  m] 40 3 0.2 V 0.4 H 21 2.0 0.2 30 2 0 V U g 0.0 1.5 0.0 0.2 0.4 0.6 0.8 Gains [dB] V DS [V] MSG/MAG 20 1 g m [mS/  m] K 1.0 10 0 K 0.5 V DS =0.5 V, V GS =0.2 V V DS = 0.5 V 0 -1 0.0 9 10 11 12 -0.6 -0.4 -0.2 0.0 0.2 10 10 10 10 V GS [V] Frequency [Hz] • High transconductance: g mpk = 1.9 mS/ μ m at V DD =0.5 V • First transistor of any kind with both f T and f max > 640 GHz (current record is f T , f max >688 GHz in Teledyne/MIT collaboration) 5 5 5

I nGaAs Electron I njection Velocity v inj E C E V Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011 • v inj (InGaAs) increases with InAs fraction in channel • v inj (InGaAs) > 2v inj (Si) at less than half V DD • ~100% ballistic transport at L g ~30 nm 6

Self-Aligned I nGaAs QW-MOSFETs • Scaled barrier (InP: 1 nm + HfO 2 : 2 nm) [EOT~0.8 nm] • 10 nm thick channel with InAs core • Tight S/D spacing (L side =20~30 nm) • Process designed to be compatible with Si fab Lin, IEDM 2012 L side 7

L g = 30 nm Self-aligned QW-MOSFET -3 320 10 At V DS =0.5 V: L g =30 nm 280 -4 10 • g m = 1.4 mS/µm 240 S (mV/dec) I D (A/  m) -5 V DS =0.5 V 10 200 • S=114 mV/dec -6 10 160 • I g <1 nA/µm -7 10 120 • R on = 470  m 50 mV 80 -8 10 -0.4 -0.2 0.0 0.2 V GS (V) Lin, IEDM 2012 8

Scaling and benchmarking 500 400 I on (  A/  m) 300 III-V FETs 200 MIT HEMT I off =100 nA/  m Planar 100 Trigate V DD =0.5 V This work 0 40 80 120 160 L g (nm) Lin, IEDM 2012 • Superior behavior to any planar III-V MOSFET to date • Matches performance of III-V Trigate MOSFETs [Radosavljevic, IEDM 2011] 9

Long-channel I nGaAs MOSFET InP (1 nm) + Al 2 O 3 (0.4 nm) + HfO 2 (2 nm)  EOT~0.9 nm Lin, IEDM 2012 • S=69 mV/dec at V DS =50 mV • Close to lowest S reported in any III-V MOSFET: 66 mV/dec (EOT=1.2 nm) [Radosavljevic, IEDM 2011] 10

Ongoing research • N-channel InGaAs MOSFETs: – Planar InGaAs MOSFET with improved access region for reduced resistance – Trigate InGaAs MOSFET with self-aligned contacts – Nanowire MOSFET with enhanced subthreshold swing – Ohmic contacts to InGaAs MOSFET • P-channel InGaSb MOSFETs: – Planar InGaSb MOSFET with uniaxial compressive strain for enhanced hole transport – Ohmic contacts to InGaSb MOSFET 11