EE3032 Introduction to VLSI Design Jin-Fu Li Department of - PDF document

Static CMOS Summary � In static circuits at every point in time (except when switching), the output is connected to either Vdd or Gnd through a low resistance path Fan-in of n (or n inputs) requires 2 n ( n N-type and n P- F i f ( i t ) i 2 ( N t d P � type) devices � Non-ratioed logic: gates operate independent of PMOS or NMOS sizes � No path ever exists between Vdd and Gnd: low static power p � Fully-restored logic (NMOS passes “0” only and PMOS passes “1” only � Gates must be inverting Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 Circuit and System Representations � Behavioral representation � Functional, high level � For documentation, simulation, verification � Structural representation � System level – CPU, RAM, I/O � Functional level – ALU, Multiplier, Adder � Gate level – AND, OR, XOR � Circuit level – Transistors, R, L, C For design & simulation � � Physical representation � For fabrication Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 15

Behavior Representation � A one-bit full adder (Verilog) module fadder(sum,cout,a,b,ci); output sum cout; output sum, cout; input a, b, ci; a b reg sum, cout; ci fadder cout always @(a or b or ci) begin sum = a^b^ci; sum cout = (a&b)|(b&ci)|(ci&a); end endmodule Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 Structure Representation � A four-bit full adder (Verilog) module adder4(s,c4,a,b,ci); a b output[3:0] sum; output c4; output c4; a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3] input[3:0] a, b; co[1] co[2] co[0] input ci; ci a0 a1 a2 a3 reg[3:0] s; s[0] s[1] s[2] s3] reg c4; wire[2:0] co; s adder4 fadder a0(s[0],co[0],a[0],b[0],ci); fadder a1(s[1] co[1] a[1] b[1] co[0]); fadder a1(s[1],co[1],a[1],b[1],co[0]); fadder a2(s[2],co[2],a[2],b[2],co[1]); fadder a3(s[3],c4,a[3],b[3],co[2]); endmodule Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 16

Physical Representation � Layout of a 4-bit NAND gate Vdd Vdd in2 in3 in4 in1 Out in1 Out in2 in3 in4 Gnd in2 in3 in4 in1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Design Flow for a VLSI Chip Specification Function Function Behavioral Design Function Structural Design Function Timing Timing Power Physical Design Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 17

Chapter 2 Chapter 2 MOS Transistor Theory MOS Transistor Theory Jin-Fu Li Ad Advanced Reliable Systems (ARES) Lab. d R li bl S t (ARES) L b Department of Electrical Engineering National Central University Jhongli, Taiwan Outline � Introduction � I-V Characteristics of MOS Transistors � Nonideal I-V Effects � Nonideal I V Effects � Pass Transistor � Summary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 1

MOS Transistor � MOS transistors conduct electrical current by using an applied voltage to move charge from the source side to the drain side of the device � An MOS transistor is a majority-carrier device m j y � In an n-type MOS transistor, the majority carriers are electrons � In a p-type MOS transistor, the majority carriers are holes � Threshold voltage It is defined as the voltage at which an MOS device begins It is defined as the voltage at which an MOS device begins � � to conduct (“turn on”) � MOS transistor symbols NMOS PMOS Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 MOS Transistor � So far, we have treated transistors as ideal switches � An ON transistor passes a finite amount of current Depends on terminal voltages � Derive current-voltage (I-V) relationships D i t lt (I V) l ti shi s � � � Transistor gate, source, drain all have capacitance I = C ( Δ V/ Δ t) -> Δ t = (C/I) Δ V � Capacitance and current determine speed � � The structure of a MOS transistor is symmetric Terminals of source and drain of a MOS can be exchanged � Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 2

V g & Channel for P-Type Body Accumulation mode Polysilicon Gate Silicon Dioxide Insulator V g <0 P-type Body Depletion mode Depletion Region 0<V g <V t Inversion mode Inversion Region V g >V t Depletion Region Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 NMOS Transistor in Cutoff Mode V gs =0 V gd g s d n + n + p-type body � Cutoff region � The source and drain have free electrons he source and dra n have free electrons � The body has free holes but no free electrons � The junction between the body and the source or drain are reverse-biased, so almost zero current flows Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 3

NMOS Transistor in Linear Mode V gs >V t V gd =V gs V gs >V t V gs >V gd >V t g g I ds s s d d n + n + n + n + n + n + n + n + p-type body p-type body V ds =0 0<V ds <V gs -V t � Linear region � A.k.a. resistive, nonsaturated, or unsaturated region � If V gd =V gs , then V ds =V gs -V gd =0 and there is no electrical field g g g g tending to push current from drain to source � If V gs >V gd >V t , then 0<V ds <V gs -V t and there is a small positive potential V ds is applied to the drain , current I ds flows through the channel from drain to source � The current increases with both the drain and gate voltage Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 NMOS Transistor in Saturation Mode V gs >V t V gd <V t g I ds s d n n + n n + p-type body V ds >V gs -V t � Saturation region � The V ds becomes sufficiently large that V gd <V t , the channel is no longer inverted near the drain and becomes pinched off � However conduction is still brought about by the drift of electrons However, conduction is still brought about by the drift of electrons under the influence of the positive drain voltage � As electrons reach the end of the channel, they are injected into the depletion region near the drain and accelerated toward the drain � The current I ds is controlled by the gate voltage and ceases to be influenced by the drain Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 4

NMOS Transistor � In summary, the NMOS transistor has three modes of operations � If V gs <V t , the transistor is cutoff and no current g flows � If V gs >V t and V ds is small, the transistor acts as a linear resistor in which the current flow is proportional to V ds � If V gs >V t and V ds is large, the transistor acts as a current source in which the current flow becomes independent of V ds � The PMOS transistor operates in just the opposite fashion Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 I-V Characteristics of MOS � In linear and saturation regions, the gate attracts carriers to form a channel � The carriers drift from source to drain at a rate proportional to the electric field between these proportional to the electric field between these regions � MOS structure looks like parallel plate capacitor while operating in inversion V g � Gate–oxide–channel N + N + Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 5

Channel Charge V g V s V d C C g V c n + n + � Q channel =C g (V gc -V t ) , where Cg is the capacitance of the gate to the channel and V gc- V t is the amount of voltage g attracting charge to the channel beyond the minimal required to invert from p to n � V c =(V s +V d )/2=V s +V ds /2 � Therefore, V gc =(V gs +V gd )/2=V gs -V ds /2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 Gate Capacitance (C g ) � Transistor dimensions t OX W Gate Gate N + N + L � The gate capacitance is WL � � = ε ε C C g ox t ox Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 6

Carrier Velocity � Charge is carried by e- � Carrier velocity v proportional to lateral E- field between source and drain � v = μ E, where μ is called mobility � E = V ds /L � Time for carrier to cross channel: � t = L / v Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 NMOS Linear I-V � Now we know � How much charge Q channel is in the channel � How much time t each carrier takes to cross � Q = channel I ds t ⎛ ⎞ W V = μ − − ⎜ ⎟ C V V V ds ⎝ 2 ⎠ ox gs t ds L ⎛ ⎞ V = β β ⎜ − − ⎜ ⎟ ⎟ V V ds V ⎝ ⎝ 2 2 ⎠ ⎠ gs gs t t ds ds W � Where β μ = C ox L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 7

NMOS Saturation I-V � If V gd <V t , channel pinches off near drain � When V ds >V dsat = V gs –V t � Now drain voltage no longer increases current � ⎛ ⎞ V = β − − ⎜ ⎟ I V V dsat V ⎝ 2 ⎠ ds gs t dsat β ( ) 2 = − V V gs t 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 Summary of NMOS I-V Characteristics ⎧ ⎪ < 0 cutoff V V ⎪ gs t ⎪ ⎛ ⎞ V = β − − < ⎨ ⎜ ⎟ linear I V V ds V V V ⎝ 2 ⎠ ds gs t ds ds dsat ⎪ ⎪ ⎪ β ( ) 2 − > saturatio n ⎪ V V V V ⎩ gs t ds dsat 2 2.5 V gs = 5 V ds =V gs -V t 2 Linear Saturation 1.5 V gs = 4 mA) I ds (m 1 V gs = 3 0.5 V gs = 2 V gs = 1 0 0 1 2 3 4 5 V ds Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 8

Example � Assume that the parameters of a technology are as follows 2.5 V gs = 5 t ox = 100 Å � 2 μ = 350 cm 2 /V*s 350 cm /V s μ � V t = 0.7 V � 1.5 V gs = 4 I ds (mA) � Plot I ds vs. V ds 1 V gs = 3 V gs = 0, 1, 2, 3, 4, 5 � 0.5 Use W/L = 4/2 λ V gs = 2 � V gs = 1 0 0 1 2 3 4 5 V ds ⎛ • ⋅ − ⎞ 14 ⎛ ⎞ 3.9 8.85 10 W W W ( ) β = μ = = μ 2 350 ⎜ ⎟ ⎜ ⎟ 120 / C A V ⋅ − ox 8 ⎝ ⎠ ⎝ ⎠ L 100 10 L L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 Nonideal I-V Effects � Nonideal I-V effects � Velocity saturation, mobility degradation, channel length modulation, subthreshold conduction, body effect, etc. � The saturation current increases less than quadratically with increasing V gs . This is caused by two effects: i h i i V Thi i d b ff � Velocity saturation � Mobility degradation � Velocity saturation � At high lateral field strengths (V ds /L), carrier velocity ceases to increase linearly with field strength � Result in lower I ds than expected at high V ds � R lt i l I th t d t hi h V � Mobility degradation � At high vertical field strengths (V gs /t ox ), the carriers scatter more often � Also lead to less current than expected at high V gs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 9

Channel Length Modulation � Ideally, I ds is independent of V ds for a transistor in saturation, making the transistor a perfect current source 1 W � = μ − 2 I C ( V V ) ds ox gs t 2 2 L L � Actually, the width L d of the depletion region between the channel and drain is increased with V db . To avoid introducing the body voltage into our calculations, assume the source voltage is close to the body voltage so V db ~V ds � Thus the effective channel length is shorten to L eff =L-L d � Therefore, the Ids can be expressed as 1 W 1 W 1 = μ − = μ − 2 2 I C ( V V ) C ( V V ) ds ox gs t ox gs t 2 2 L L L − 1 d eff L � Assume that , then L d << 1 L 1 1 W L W = μ − + = μ − + λ 2 2 ( ) (1 d ) ( ) (1 ) I C V V C V V V ds ox gs t ox gs t ds 2 2 L L L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 Channel Length Modulation � The parameter is an empirical channel length λ modulation factor � As channel length gets shorter, the effect of the channel length modulation becomes relatively more channel length modulation becomes relatively more important � Hence is inversely dependent on channel length λ � This channel length modulation model is a gross oversimplification of nonlinear behavior and is more useful for conceptual understanding than for accurate device modeling device modeling � Channel length modulation is very important to analog designers because it reduces the gain of amplifiers. It is generally unimportant for qualitatively understanding the behavior of digital circuits Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 10

Body Effect � Body effect V t is a function of voltage between source and substrate � 0 9 0.9 0.85 0.8 0.75 0.7 V T (V) 0.65 0.6 0.55 0.5 0.45 Degree 0.4 -2.5 -2 -1.5 -1 -0.5 0 Low High V BS (V) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 Mobility Variation μ � Mobility � It describes the ease with which carriers drift in the substrate material � It i d fi � It is defined by d b μ =(average carrier drift velocity, v )/(electrical field, E) � � Mobility varies according to the type of charge carrier � Electrons have a higher mobility than holes � Thus NMOS has higher current producing capability than � Thus NMOS has higher current-producing capability than the corresponding PMOS � Mobility decreases with increasing doping- concentration and increasing temperature Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 11

Drain Punchthrough & Hot Electrons � Drain punchthrough � When the drain voltage is high enough, the depletion region around the drain may extend to source. Thus, causing current to flow irrespective Th i t t fl i ti of the gate voltage � Hot electrons � When the source-drain electric field is too large, the electron speed will be high enough to break the electron-hole pair. Moreover, the electrons p , will penetrate the gate oxide, causing a gate current Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 Subthreshold Conduction � Subthreshold region The cutoff region is also referred to as the subthreshold � region, where I ds increases exponentially with V ds and V gs Observe in the following figure that at V gs V t , the current Observe in the following figure that at V gs <V t , the current � drops off exponentially rather than abruptly becoming zero I ds Saturation V ds =1.8 1 mA Subthreshold region 100 uA region 10 uA 1 uA 100 nA 10 nA Subthreshold slope 1 nA 100 pA V t 10 pA 0 0.3 0.6 0.9 1.2 1.5 1.8 V gs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 12

Junction Leakage � The p-n junctions between diffusion and the substrate or well form diodes � The p-type and n-type substrates are tied to GND or V dd to ensure these diodes remain reverse-biased � However, reverse-biased diodes still conduct a small amount of current I L V D , V D : diode voltage; v T : thermal voltage � = − v ( 1 ) I I e T L S (about 26mv at room temperature) � In modern transistors with low threshold voltages, subthreshold conduction far exceeds junction leakage N + N + Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 Temperature Dependence � The magnitude of the threshold voltage decreases nearly linearly with temperature � Carrier mobility decreases with temperature � Junction leakage increases with temperature because � Junction leakage increases with temperature because I s is strongly temperature dependent � The following figure shows how the current I dsat decreases with temperature 250 240 I dsat (uA) 230 220 210 0 20 40 60 80 100 120 Temperature (C) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 13

Geometry Dependence � The layout designer draws transistors with width and length W draw and L draw . The actual gate dimensions may differ by some factors X W and X L E.g., the manufacturer may create masks with narrower � polysilicon or may overetch the polysilicon to provide shorter channels (negative X L ) � Moreover, the source and drain tend to diffuse laterally under the gate by L D , producing a shorter effective channel length that the carriers must traverse between source and drain. Similarly, diffusion of the bulk by W D decreases the effective channel width decreases the effective channel width � Therefore, the actually effective channel length and width can be expressed as L eff =L draw +X L -2L D � W eff =W draw +X W -2W D � Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 MOS Small Signal Model (V sb =0) C gd Gate Drain g ds C gs +C gb g m V gs C db Source Linear region Saturation region W 1 1 W = μ − − 2 = μ μ − I C [( V V ) V V ] 2 ( ( ) ) I C V V ds ox gs g t ds ds ds ds ox ox gs gs t t L L 2 2 2 2 L L dI W = = μ − − = ds g C [( V V ) V ] g 0 ds ox gs t ds ds dV L ds W dI W = μ − = = = μ ( ) ds | ( .) g C V V g V const C V m ox gs t m ds ox ds L dV L gs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 14

Pass Transistor � NMOS pass transistor C load is initially discharged, i.e., V out =V ss � If V in =V dd and V S =V dd , the V out =V dd -V tn � If V in =V ss and V S =V dd , the V out =V ss � V out V in C load S � PMOS pass transistor If V in =V dd and V -S =V ss , the V out =V dd � If V in =V ss and V S =V ss the V out =V tp If V in V ss and V -S V ss , the V out V tp � � V out V in C load -S Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 Pass Transistor Circuits V V V DD DD DD V V V DD DD V DD V DD -V V s = V DD -V V DD -V tn V DD -V tn tn tn V DD V DD -V V s = |V tp | tn V V V DD -2V DD 2V DD DD tn V SS Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 15

Transmission Gate � By combining behavior of the NMOS and PMOS, we can construct a transmission gate The transmission gate can transmit both logic one and logic � zero without degradation g -S V out V in C load S � The transmission gate is a fundamental and ubiquitous component in MOS logic p g A multiplexer element � A logic structure, � A latch element, etc. � Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 Voltage-Controlled Resistor � Consider the case where the control input changes rapidly, the V in is V dd , and the capacitor on the transmission gate output is discharged (V ss ) The transmission gate acts as a resistor he transm ss on gate acts as a res stor � mA I d -S I dn +I dp V dd V out V DD V ss I d I dp C load C S I dn 1 2 3 4 5 V out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 16

Summary � Threshold drops Pass transistors suffer a threshold drop when passing the � wrong value: NMOS transistors only pull up to V DD -V tn , while PMOS transistors only pull down to |V tp | The magnitude of the threshold drop is increased by the � body effect Fully complementary transmission gates should be used � where both 0’s and 1’s must be passed well � V DD Velocity saturation and mobility degradation result in less � current than expected at high voltage current than expected at high voltage This means that there is no point in trying to use a high V DD � to achieve high fast transistors, so V DD has been decreasing with process generation to reduce power consumption Moreover, the very short channels and thin gate oxide would � be damaged by high V DD Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Summary � Leakage current Real gates draw some leakage current � The most important source at this time is subthreshold leakage � between source and drain of a transistor that should be cut off The subthreshold current of a OFF transistor decreases by an The subthreshold current of a OFF transistor decreases by an � � order of magnitude for every 60-100mV that V gs is below V t . Threshold voltages have been decreasing, so subthreshold leakage has been increasing dramatically Some processes offer multiple choices of V t ; low-V t devices are � used for high performance, while high-V t devices are used for low leakage elsewhere Leakage current causes CMOS gates to consume power when idle Leakage current causes CMOS gates to consume power when idle. � � It also limits the amount of time that data is retained in dynamic logic, latches, and memory cells In modern processes, dynamic logic and latches require some � sort of feedback to prevent data loss from leakage Leakage increases at high temperature � Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 17

Chapter 3 Chapter 3 Fabrication of CMOS Fabrication of CMOS Integrated Circuits Integrated Circuits Integrated Circuits Integrated Circuits Jin-Fu Li Department of Electrical Engineering D f El i l E i i National Central University Jungli, Taiwan Outline � Background � The CMOS Process Flow � Design Rules � Design Rules � Latchup � Antenna Rules & Layer Density Rules � CMOS Process Enhancements � Summary � Summar � 3D Integration Technology Using TSV Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 1

Introduction � An integrated circuit is created by stacking layers of various materials in a pre-specified sequence � Both the electrical properties of the material and the geometrical patterns of the layer are important in establishing the characteristics of devices and networks � Most layers are created first, and then patterned using lithographic sequence tt d i lith hi � Doped silicon layers are the exception to this rule Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Material Growth and Deposition � Silicon Dioxide (SiO 2 ) � It is an excellent electrical insulator � It can be grown on a silicon wafer or deposited on t top of the wafer f th f � Thermal oxide � Si+O 2 � SiO 2 (dry oxidation), using heat as a catalyst Growth rate is lower � � Si+2H 2 O � SiO 2 +2H 2 (wet oxidation) Growth rate is faster � � The surface of the silicon is recessed from its original � The surface of the silicon is recessed from its original location � CVD oxide � SiH 4 (gas)+2O 2 (gas) � SiO 2 (solid)+2H 2 O(gas) � Chemical vapor deposition (CVD) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 2

Material Growth and Deposition � Silicon Nitride (Si 3 N 4 ) � A.k.a. nitride � 3SiH 4 (gas)+4NH 3 (gas) � Si 3 N 4 (solid)+12H 2 (gas) � Nitrides act as strong barriers to most atoms, this makes them ideal for use as an overglass layer � Polycrystal Silicon � Called polysilicon or just poly for short � It is used as the gate material in MOSFETs � SiH 4 � Si+2H 2 � SiH � Si 2H � It adheres well to silicon dioxide Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Material Growth and Deposition � Metals � Aluminum (Al) is the most common metal used for interconnect wiring in ICs � It is prone to electromigration � It is pr ne t electr mi rati n � J=I/A; A=wt is the cross-section area � Layout engineers cannot alter the thickness t of the layer � Electromigration is thus controlled by specifying the minimum width w to keep J below a max. value � Copper (Cu) has recently been introduced as a pp ( ) y replacement to aluminum � Its resistivity is about one-half the value of Al � Standard patterning techniques cannot be used on copper layers; specialized techniques had to be developed Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 3

Material Growth and Deposition � Doped Silicon Layers Silicon wafer is the starting point of the CMOS fabrication � process A doped silicon layer is a patterned n- or p-type section of p y p p yp � the wafer surface This is accomplished by a technique called ion implantation � � Basic section of an ion implanter Ion source Magnetic Mass Accelerator Separator Ion beam wafer Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 Material Growth and Deposition � The process of deposition causes that the top surface has hillocks If we continue to add layers (e.g., metal layers), the surface � will get increasing rough and may lead to breaks in fine line g g g y features and other problems Surface planarization is required � � Chemical-Mechanical Polishing (CMP) It uses a combination of chemical etching and mechanical � sanding to produce planar surfaces on silicon wafers � Surface planarization poly substrate substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 4

Lithography � One of the most critical problems in CMOS fabrication is the technique used to create a pattern � Photolithography l � The photolithographic process starts with the desired pattern definition for the layer � A mask is a piece of glass that has the pattern defined using a metal such as chromium h i Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 Transfer a Mask to Silicon Surface � The process for transferring the mask pattern to the surface of a silicon region � Coat photoresist � Coat photoresist � Exposure step � Etching � Coat photoresist � Liquid photoresist is sprayed onto a spinning wafer � Exposure � Exposure � Photoresist is sensitive to light, such as ultraviolet (UV) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 5

Transfer a Mask to Silicon Surface The figure shown as below depicts the main idea � UV Hardened mask a resist layer resist layer photoresist wafer wafer The hardened resist layer is used to protect underlying � regions from the etching process � E � Etching hi The chemicals are chosen to attack and remove the material � layer not shielded by the hardened photoresist Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 Dopping The figure shows the etching process � Hardened Patterned resist layer oxide layer Oxide layer Substrate Substrate � Creation of doped silicon Arsenic ions Lateral dopping N+ N+ Substrate Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 6

Dopping � The conductive characteristics of intrinsic silicon can be changed by introducing impurity atoms into the silicon crystal lattice � Impurity elements that use (provide) electrons are called as acceptor (donor) � Silicon that contains a majority of donors (acceptor) is known as n-type (p-type) � When n-type and p-type materials are merged together, the region where the silicon changes from n-type to p-type is called junction Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 MOS Transistor � Basic structure of a NMOS transistor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 7

Fabrication Steps for an NMOS n + n + Implant or Patterning Diffusion SiO 2 Layer Implant of p p-substrate p-substrate p-substrate Impurities Thin Oxide SiO 2 by Contact n + n + Gate deposition Cuts Oxidation p-substrate p-substrate Polysilicon Al contacts n + n + Patterning Patterning Polysilicon Al layer p-substrate p-substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 Basic CMOS Technology � Four dominant CMOS technologies � N-well process � P-well process � Twin-tub process � Silicon on insulator (SOI) � N-well (P-well) process � Starts with a lightly doped p-type (n-type) substrate (wafer), create the n-type (p-type) well for the p-channel (n-channel) devices, and build f th h l ( h l) d i d b ild the n-channel (p-channel) transistor in the native p-substrate (n-substrate) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 8

N-Well CMOS Process Mask (top view) Cross Section of Physical Structure n-well mask n-well p-substrate n-well active mask nitride oxide n-well p-substrate Active Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 N-Well CMOS Process Resist Implant (Boron) channel stop mask p-channel stop n-well p-substrate Channel stop n-well p-substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 9

N-Well CMOS Process polysilicon mask n-well p-substrate polysilicon n + mask n + n + n-well p-substrate n + mask Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 N-Well CMOS Process Light implant heavier implant oxide poly poly poly n - n - n - n - n + n + Shadow drain implant LDD (lightly doped drain) structure p + mask n + n + p + p + n-well p-substrate p + mask Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 10

N-Well CMOS Process contact mask n + n + p + p + n-well p-substrate contact mask metal mask n + n + p + p + n-well p-substrate metal mask Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 CMOS Inverter in N-Well Process in out Vdd Vss in out Vdd Vss Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 11

CMOS Inverter in N-Well Process p + p p + p n + n + n + n + n-well p-substrate field oxide metal gate oxide polysilicon contact cut p + p + n + n + n-well p-substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 A Sample of Multi-Layer Metal Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 12

Design Rules � Design rules (layout rules) � Provide a necessary communication link between circuit designers and process engineers during manufacturing phase f t i h � The goal of design rules is to achieve the optimum yield of a circuit with the smallest area cost � Design rules specify to the designer certain geometric constraints on the layout artwork so that the patterns on the processed wafer so that the patterns on the processed wafer will preserve the topology and geometry of the designs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 Design Rules � The design rules primarily address two issues � The geometrical reproduction of features that can be reproduced by the mask-making and lith lithographical process hi l � The interactions between different layers � Lambda-based rules � Based on a single parameter, lambda, which characterizes the linear feature – the resolution of the complete wafer implementation process of the complete wafer implementation process Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 13

Examples of Design Rules Different Potential Same Potential 9 0 W ll Well or 6 10 3 2 Active Polysilicon 3 2 3 3 Metal1 Contact or Via 2 Hole 3 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 Transistor Layout or ransisto 1 T 3 2 5 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 14

Design Rules for Vias & Contacts 2 4 Via 1 1 1 1 5 Metal to Poly Contact Metal to 1 Active Contact 3 2 2 2 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 Design Rule Checker Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 15

Latchup � Latchup is defined as the generation of a low- impedance path in CMOS chips between power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors � These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to ground, th thus causing excessive current flows and even i i t fl d permanent device damage Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 Latchup of a CMOS Inverter Vdd p + n + n + p + p + n + PNP NPN N-well R well well R substrate P-substrate 2.0mA R well I I ramp Trigger point V ne R substrate I ramp -1 0 1 2 3 4 Holding Voltage V ne Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 16

Latchup Triggering � Latchup can be triggered by transient current or voltages that may occur internally to a chip during power-up or externally due to voltages or currents beyond normal operating ranges t b d l ti � Two possible triggering mechanisms � Lateral triggering & vertical triggering � Ex: the static trigger point of lateral triggering is V − ≈ pnp on I α ntrigger R npn well Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Latchup Prevention � Reducing the value of resistors and reducing the gain of the parasitic transistors are the basis for eliminating latchup � Latchup can be prevented in two basic methods � Latchup resistant CMOS process � Layout techniques � I/O latchup prevention p p � Reducing the gain of parasitic transistors is achieved through the use of guard rings Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 17

Guard Rings � Guard rings are that p+ diffusions in the p- substrate and n+ diffusions in the n-well to collect injected minority carriers Vdd emitter p + p-plus l n-plus n + n-plus base collector N-well (substrate) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 I/O Latchup Prevention � A p+ guard ring is shown below for an n+ source/drain V ss n+ p+ p+ + + + hole current + N-well P+ collects hole current thereby shielding n+ source/drain � A n+ guard ring is shown below for a p+ source/drain V dd n+ collects electron current dd th thereby shielding p+ b hi ldi + source/drain n+ n+ p+ - electron current - - N-well Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 18

Antenna Rules � When a metal wire contacted to a transistor gate is plasma-etched, it can charge up to a voltage sufficient to break down thin gate oxide � The metal can be contacted to diffusion to provide a � The metal can be contacted to diffusion to provide a path for the charge to bleed away � Antenna rules specify the maximum area of metal that can be connected to a gate without a source or drain to act as a discharge element � The design rule normally defines the maximum ratio of metal area to gate area such that charge on the f t l t t h th t h th metal will not damage the gate The ratios can vary from 100:1 to 5000:1 depending on the � thickness of the gate oxide (and hence breakdown voltage) of the transistor in question Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Antenna Rule Violation and Fix Wire attracts charge during plasma processing and builds up voltage V=Q/C L2 Any source/drain can act as a Length L2 exceeds allowed limit discharge element discharge element Gate may be connected to source/drain at any metal layer in an auto routing situation metal 4 metal 3 L1 metal 2 metal 1 Added link solves problem-L1 satisfies design rule Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 19

Antenna Diode Addition � An alternative method is to attach source/drain diodes to problem nets as shown below These diodes can be simple junctions of n-diffusion to p- � substrate rather than transistor source/drain regions L2 Antenna diode may be added Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39 Layer Density Rules � For advanced processes, a minimum and maximum density of a particular layer within a specific area should be specified Layer density rules � � Layer density rules are required as a result of the CMP process and the desire to achieve uniform etch rates � For example, a metal layer might have to have 30% minimum and 70% maximum fill within a 1mm by 1mm area � For digital circuits layer density levels are normally � For digital circuits, layer density levels are normally reached with normal routing � Analog & RF circuits are almost sparse Gate and metal layers may have to be added manually or by a � fill program after design has been completed Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40 20

CMOS Process Enhancements � Multiple threshold voltages Low-V t → more on current, but greater subthreshold leakage � High-V t → less current, but smaller subthreshold leakage � User low-V t devices on critical paths and higher-V t devices p g � t t elsewhere to limit leakage power Multiple masks and implantation steps are used to set the � various thresholds � Silicon on insulator (SOI) process The transistors are fabricated on an insulator � Two major insulators are used, SiOs and sapphire � Two major advantages: elimination of the capacitance between T j d t li i ti f th it b t � the source/drain regions and body, leading to higher-speed devices; lower subthreshold leakage Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41 CMOS Process Enhancements � High-k gate dielectrics MOS needs high gate capacitance to attract charge to � channel → very thin SiO 2 gate dieletrics � Scaling trends indicate the gate leakage will be � Scaling trends indicate the gate leakage will be unacceptably large in such thin gates Gates could use thicker dielectrics and hence leak less if a � material with a higher dielectric constant were available Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42 21

Summary � Some of more common CMOS technologies have been covered � A representative set of n-well process has p p been introduced � Concepts of design rules have been presented � The important condition known as latchup has been introduced with necessary design rules to avoid this condition in CMOS chips p � Antenna rules & layer density rules should be considered in modern manufacturing process Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43 3D Integration Technology � 3D integration approaches 3D packaging technology � 3D integration using through silicon via (TSV) � � 3D packaging technology � 3D k i h l Source: Proceedings of IEEE, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44 22

3D Integration Technology � 3D integration using TSV Via-last technology � Via-first technology � � Vi � Via-First Fi (1) Before CMOS (2) After CMOS & BEOL (2) After CMOS & BEOL Source: Yole, 2007. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45 3D Integration Technology � Via-Last (1) After BEOL & before bonding (2) After bonding Source: Yole, 2007. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46 23

3D Integration Technology Source: ASP-DAC 2009. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47 Fabrication Flow Source: ASP-DAC 2009. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 24

Design Example Source: ASP-DAC 2009. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49 Benefits of 3D Integration � Benefits of 3D integration over 2D integration High functionality � High performance H h f � Small form factor � Low power � Source: Proceedings of IEEE, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50 25

Road Map of 3D Integration with TSVs Source: Proceedings of IEEE, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51 26

Chapter 4 Chapter 4 Electrical Characteristics Electrical Characteristics of CMOS of CMOS of CMOS of CMOS Jin-Fu Li Department of Electrical Engineering Department of Electrical Engineering National Central University Jungli, Taiwan Outline � Resistance & Capacitance Estimation � DC Response � Logic Level and Noise Margins � Transient Response � Delay Estimation � Transistor Sizing � Power Analysis � Scaling Theory Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 1

Resistance Estimation � Resistance , where is ( resistivity , ρ � = ρ ( , , , ) t L W ( / )( / ) R t L W thickness, conductor length, conductor width ) � Sh � Sheet resistance i = Ω � / R □ s � Thus = ( / ) R R L W s W W t 1 rectangular block = ( / ) R R L W s L L W W t L L 4 rectangular block = = R R ( 2 L / 2 W ) R ( L / W ) s s Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Drain-Source MOS Resistance � A simplified linear model of MOS is useful at the logic level design � RC model of an NMOS G R R n G S D C s C D S D � The drain-source resistance at any point on the current curve as shown below I ds c b a V ds Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 2

Drain-Source Resistance � The resistance at point a � The current is approximated by ≈ β − ( ) � I V V V ds n gs g t ds � Thus the resistance is ≈ β − � R 1 / ( V V ) n n gs t � The resistance at point b � The full non-saturated current must be used so that 1 = β β − − 2 [ [ 2 2 ( ( ) ) ] ] I I V V V V V V V V � � d ds n gs t ds d ds d 2 � Thus the resistance is = β − − 2 / [ 2 ( ) ] R V V V � n n gs t ds Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Drain-Source Resistance � The resistance at point c � The current is 1 � ≈ β − 2 ( ) I V V ds n gs t 2 � Thus the resistance is � Thus the resistance is = β − � 2 2 / ( ) R V V V n ds n gs t � R n is a function of both V gs and V ds � These equations show that it is not possible to define a constant value for R n � However R is inversely proportion to in all � However, R n is inversely proportion to in all β β n cases, i.e., ∝ β � 1 / R n n , W/L is called aspect ratio β n = � ( / ) k W L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 3

Capacitance Estimation � The switching speed of MOS circuits are heavily affected by the parasitic capacitances associated with the MOS device and i t interconnection capacitances ti it � The total load capacitance on the output of a CMOS gate is the sum of � Gate capacitance � Diffusion capacitance � Routing capacitance � R ti it � Understanding the source of parasitic loads and their variations is essential in the design process Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 MOS-Capacitor Characteristics � The capacitance of an MOS is varied with the applied voltages � Capacitance can be calculated by p y ε 0 ε � = x C A d ε is dielectric constant � x ε is permittivity of free space � 0 � Depend on the gate voltage, the state of the MOS surface may be in y � Accumulation � Depletion � Inversion Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 4

MOS Capacitor Characteristics � When V g <0, an accumulation layer is formed � The negative charge on the gate attracts holes toward the silicon surface � The MOS structure behaves like a parallel-plate � Th MOS t t b h lik ll l l t capacitor gate gate V g <0 ε 0 ε t ox C o 0 = o 0 SiO 2 SiO 2 C C A A t ox P-substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 MOS Capacitor Characteristics � When a small positive voltage is applied to the gate, a depletion layer is formed � The positive gate voltage repels holes, leaving a negatively charged region depleted of carriers ti l h d i d l t d f i gate gate V g ~0 ε 0 ε = Si C A dep d t ox C o Depletion layer d C C dep C C = 0 dep C + gb P-substrate C C 0 dep Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 5

MOS Capacitor Characteristics � When the gate voltage is further increased, an n-type channel (inversion layer) is created � If the MOS is operated at high frequency, the surface charge is not able to track fast moving f h i t bl t t k f t i gate voltages gate gate V g >0 Low frequency C gb = C 0 t ox C o Channel Depletion layer Depletion layer C dep C Hi h f High frequency C C = = 0 dep P-substrate C C + gb min C C 0 dep Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 MOS Capacitor Characteristics � Consequently, the dynamic gate capacitance as a function of gate voltage, as shown below Accumulation Depletion Inversion Accumulation Depletion Inversion 1.0 Low freq. C/C o High freq. V gs V gs V V t 0 0 � The minimum capacitance depends on the depth of the depletion region, which depends on the substrate doping density Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 6

MOS Device Capacitances � The parasitic capacitances of an MOS transistor are shown as below � C gs , C gd : gate-to-channel capacitances, which are l lumped at the source and the drain regions of the d t th d th d i i f th channel, respectively � C sb , C db : source and drain-diffusion capacitances to bulk � C gb : gate-to-bulk capacitance C gd C db gate C gs C gb C gd channel source drain depletion layer C gs C sb C gb C sb C db substrate C g =C gb +C gs +C gd Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 Variation of Gate Capacitance � The behavior of the gate capacitance in the three regions of operation is summarized as below � Off region (V gs <V t ): C gs =C gd =0; C g =C gb � Non-saturated region (V gs -V t >V ds ): C gs and C gd become significant. These capacitances are dependent on gate voltage. Their value can be estimated as ε ε 1 = = 0 SiO C C C C 2 A A gd d gs 2 t ox � Saturated region (V gs -V t <V ds ): The drain region is pinched off, causing C gd to be zero. C gs increases to approximately ε ε 2 = o SiO C 2 A gs 3 t ox Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 7

Approximation of the C g � The C g can be further approximated with ε ε , where � g = = o SiO C C A C 2 ox ox t � The gate capacitance is determined by the ox gate area, since the thickness of oxide is associated with process of fabrication � For example, assume that the thickness of silicon oxide of the given process is . × − μ 8 150 10 m Calculate the capacitance of the MOS shown below b l λ λ 2 2 λ = μ 0 . 5 m λ 4 λ 5 × × − 14 3 . 9 8 . 854 10 = × = × × − ≈ 4 2 25 . 5 2 10 0 . 005 C g pF pF × − 8 150 10 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 Diffusion Capacitance � Diffusion capacitance C d is proportional to the diffusion-to-substrate junction area Substrate b Source Drain a Diffusion Diffusion b Area Area a C jp X c (a finite depth) C ja = × + × + ( ) ( 2 2 ) C C ab C a b d ja jp C ja =junction capacitance per micron square C jp =periphery capacitance per micron Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 8

Junction Capacitance � Semiconductor physics reveals that a PN junction automatically exhibits capacitance due to the opposite polarity charges involved. This is called junction or depletion This is called junction or depletion capacitance and is found at every drain or source region of a MOS � The junction capacitance is varies with the junction voltage, it can be estimate as V V − = − j m ( 1 ) C C 0 j j V b =junction voltage (negative for reverse bias) � C j =zero bias junction capacitance ( ) = � C 0 V 0 j j =built-in junction voltage � V ~ 0 . 6 V b Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 Single Wire Capacitance � Routing capacitance between metal and substrate can be approximated using a parallel-plate model Fringing fields W L T H Insulator (Oxide) ( ) substrate substrate � In addition, a conductor can exhibit capacitance to an adjacent conductor on the same layer Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 9

Multiple Conductor Capacitances � Modern CMOS processes have multiple routing layers � The capacitance interactions between layers can become quite complex � Multilevel-layer capacitance can be modeled as below Layer 3 C 23 C 22 Multi-layer Layer 2 Layer 2 conductor d t C 21 Layer 1 C 2 =C 21 +C 23 +C 22 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 A Process Cross Section � Interlayer capacitances of a two-level-metal process A A B B C C D D E E F F G G m2 m2 m2 m2 m2 C m2 C m1 m1 C m1 C C C C poly poly poly poly C C C Thin-oxide/diffusion Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 10

Inductor � For bond wire inductance μ 4 h � d = h L ln( ) π 2 d w w � For on-chip metal wires μ 8 � h w = π + ln( ) L h 2 4 w h � The inductance produces Ldi/dt noise especially for ground bouncing noise. Note that when CMOS circuit are clocked, the current flow changes greatly di V = L dt Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 Distributed RC Effects � The propagation delay of a signal along a wire mainly depends on the distributed resistance and capacitance of the wire � A long wire can be represented in terms of several RC sessions, as shown below I j-1 I j R R R V j R V j+1 R V j-1 C C C C C � The response at node V j with respect to time is then given by − − ( ) ( ) dV V V V V � − + = ⇒ = − = − j j 1 j j j 1 CdV Idt C ( I I ) − 1 j j dt R R Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 11

Distributed RC Effects � As the number of sections in the network becomes large (and the sections become small), the above expression reduces to the diff differential form ti l f 2 dV d V = ⇒ x = � 2 rc t kx 2 dt dx � r : resistance per unit length � c : capacitance per unit length � Alternatively, a discrete analysis of the circuit shown in the previous page yields an ci cuit sh n in th p vi us p i lds n approximate signal delay of + ( 1 ) RCn n , where n=number of sections � = × t n 0 . 7 2 2 rcl � t = 0 . 7 1 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 Wire Segmentation with Buffers � To optimize speed of a long wire, one effective method is to segment the wire into several sections and insert buffers within these sections th ti � Consider a poly bus of length 2mm that has been divided into two 1mm sections. � Assume that = × − 15 2 t x 4 10 x � With buffer = × − × + + × − × 15 2 15 2 t 4 10 1000 t 4 10 1000 p buf = + + + + = + + 4 4 4 4 8 8 ns ns t t ns ns ns ns t t buf b f b f buf � Without buffer − = × × = 15 2 4 10 2000 16 t p ns � By keeping the buffer delay small, significant gain can be obtained with buffer insertion Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 12

Crosstalk � A capacitor does not like to change its voltage instantaneously. � A wire has high capacitance to its neighbor. � When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. � Called capacitive coupling or crosstalk . � Crosstalk effects � Noise on nonswitching wires � Increased delay on switching wires d d l h Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 Crosstalk Delay � Assume layers above and below on average are quiet � Second terminal of capacitor can be ignored � Model as C gnd = C top + C bot � Effective C adj depends on behavior of neighbors � Miller effect Δ V B C eff(A) MCF A A B B Constant V DD C gnd + C adj 1 C adj Switching with A 0 C gnd 0 C gnd C gnd Switching opposite A 2V DD C gnd + 2 C adj 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 13

Crosstalk Noise � Crosstalk causes noise on nonswitching wires � If victim is floating: � model as capacitive voltage divider C Δ = Δ adj V V + victim aggressor C C − gnd v adj Aggressor Δ V aggressor C adj Victim Δ V victim C gnd-v Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 Driven Victim � Usually victim is driven by a gate that fights noise � Noise depends on relative resistances � Victim driver is in linear region, agg. in saturation � If sizes are same, R aggressor = 2-4 x R victim C 1 Δ = Δ adj V V R aggressor + + victim aggressor Aggressor 1 C C k − gnd v adj C gnd-a Δ V aggressor C adj adj ( ) R victim Victim τ + R C C Δ V victim − C gnd-v = = aggressor aggressor gnd a adj k ( ) τ + R C C − victim victim gnd v adj Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 14

Simulation Waveforms � Simulated coupling for C adj = C victim Aggressor 1.8 1.5 1.2 Victim (undriven): 50% 0.9 0.6 Victim (half size driver): 16% Victim (equal size driver): 8% 0.3 Victim (double size driver): 4% 0 0 200 400 600 800 1000 1200 1400 1800 2000 t (ps) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 DC Response � DC Response: V out vs. V in for a gate � Ex: Inverter � When V in = 0 � V out =V DD in out DD V DD � When V in = V DD � V out =0 � In between, V out depends on I dsp transistor size and current V in V out � By KCL, must settle such that I dsn I dsn = |I dsp | p � We could solve equations � But graphical solution gives more insight Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 15

Transistor Operation � Current depends on region of transistor behavior � For what V in and V out are NMOS and PMOS For what V in and V out are NMOS and MOS in � Cutoff? � Linear? � Saturation? Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 NMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn – V tn V dsn > V gsn – V tn V DD I dsp I V gsn = V in V in V out I dsn V dsn = V out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 16

NMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V i < V t V in < V tn V i > V t V in > V tn V in > V tn V i > V t V dsn < V gsn – V tn V dsn > V gsn – V tn V out < V in - V tn V out > V in - V tn V DD V V gsn = V in V I I dsp V in V out V dsn = V out I dsn Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 PMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp – V tp V dsp < V gsp – V tp V DD I dsp V gsp = V in - V DD V = V V V < 0 V tp < 0 dsp V V in V out V V dsp = V out - V DD I dsn Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 17

PMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V in > V DD + V tp V in < V DD + V tp V in < V DD + V tp V dsp > V gsp – V tp V dsp < V gsp – V tp V out > V in - V tp V out < V in - V tp V DD V V gsp = V in - V DD = V V V tp < 0 V < 0 I dsp I V in V out V dsp = V out - V DD I dsn Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 I-V Characteristics � Make pMOS is wider than nMOS such that β n = β p V gsn5 V gsn4 I dsn V gsn3 -V dsp V gsn2 -V DD V gsp1 V gsn1 V gsp2 0 V DD V V dsn V V gsp3 V gsp4 -I dsp V gsp5 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 18

Current & V out , V in V in1 V in5 V in2 V in4 I dsn , |I dsp | V in3 V in3 V in4 V in2 in4 in2 V in5 V in1 V DD V out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Load Line Analysis � For a given V in : � Plot I dsn , I dsp vs. V out � V out must be where |currents| are equal in V in1 V in5 V in2 V in4 V DD I dsn , |I dsp | I dsp V in V V V out V V in3 V V in3 I dsn V in4 V in2 V in5 V in1 V DD V out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 19

DC Transfer Curve � Transcribe points onto V in vs. V out plot V in1 V in5 V in2 V in4 V in3 V in3 V in4 V in2 V in5 V in1 V DD V out V DD A B V out C D E 0 V tn V DD /2 V DD +V tp V DD V in Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39 Operation Regions � Revisit transistor operating regions Region nMOS pMOS V DD A B A Cutoff Linear B Saturation Linear V out C C Saturation Saturation D Linear Saturation D D E Linear Cutoff E 0 V tn V DD /2 V DD +V tp V DD V in Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40 20

Beta Ratio � If β p / β n ≠ 1, switching point will move from V DD /2 � Called skewed gate � Other gates: collapse into equivalent inverter V DD β β = p 10 n V out 2 1 0.5 β β = p 0.1 n 0 V DD V in Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41 Noise Margin � How much noise can a gate input see before it does not recognize the input? Output Characteristics Input Characteristics V DD Logical High V OH Logical High Output Range Input Range NM H V IH Indeterminate Region Region V IL V NM L Logical Low Logical Low V OL Input Range Output Range GND Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42 21

Transient Analysis � DC analysis tells us V out if V in is constant � Transient analysis tells us V out (t) if V in (t) changes g Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43 Switching Characteristics � Switching characteristics for CMOS inverter V (t) V in (t) V V out (t) (t) V ds =V gs -V t C L V DD I ds V in (t) t t df t dr V DD 90% V out (t) V DD V out (t) 50% 10% t t f t r Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44 22

Switching Characteristics � Rise time (t r ) � The time for a waveform to rise from 10% to 90% of its steady-state value � Fall time (t ) � Fall time (t f ) � The time for a waveform to fall from 90% to 10% steady-state value � Delay time (t d ) � The time difference between input transition (50%) and the 50% output level (This is the time (50%) and the 50% output level. (This is the time taken for a logic transition to pass from input to output � High-to-low delay (t df ) � Low-to-high delay (t dr ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45 Fall Time of the Inverter � Equivalent circuit for fall-time analysis PMOS PMOS V out (t) V out (t) Input rising R cn I dsn NMOS NMOS C L C L Nonsaturated 0<V out <=V DD -V tn Saturated V out >=V DD -V tn � The fall time consists of two intervals � t f1 =period during which the capacitor voltage, V out , � t i d d i hi h th it lt V drops from 0.9V DD to (V DD -V tn ) � t f2 =period during which the capacitor voltage, V out , drops from (V DD -V tn ) to 0.1V DD Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46 23

Timing Calculation � t f1 can be calculated with the current-voltage equation as shown below, while in saturation β 2 = dV + − � out n C ( V V ) 0 L DD tn 2 2 dt dt � t f2 also can be obtained by the same way � Finally, the fall time can be estimated with C ≈ × L t k β f V � Similarly, the rise time can be estimated with n DD C � ≈ × L t k β r V � Thus the propagation delay is p p DD C 1 1 � ≈ × β + t k L ( ) β p V DD n p Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47 Design Challenges β β = , rise time=fall time � p n � This implies W p =2-3W n � Reduce C L L � Careful layout can help to reduce the diffusion and interconnect capacitance β � Increase β and n p � Increase the transistor sizes also increases the diffusion capacitance as well as the gate capacitance. The latter will increase the fan-out factor of the The latter will increase the fan out factor of the driving gate and adversely affect its speed � Increase V DD � Designers don ’ t have too much control over this Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 24

Gate Delays � Consider a 3-input NAND gate as shown below P 3 P 2 P 1 out IN-3 IN 3 N N 3 IN-2 N 2 IN-1 N 1 � When pull-down path is conducting 1 β = � neff β + β + β ( 1 / ) ( 1 / ) ( 1 / ) 1 2 3 n n n β � For β = β = β ⇒ β = n n 1 n 2 n 3 neff 3 � When the pull-down path is conducting � Only one p-transistor has to turn on to raise the output. Thus β = β peff p Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49 Gate Delays � Graphical illustration of the effect of series transistors L L 3L L w w � In general, the fall time t f is mt f (t f /m) for m n- � In n l th f ll tim t is mt (t /m) f m n transistors in series (parallel). Similarly the rise time t r for k p-transistors in series (parallel) is kt r (t r /k) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50 25

Switch-Level RC Model � RC modeling � Transistors are regarded as a resistance discharging or charging a capacitance � Simple RC modeling � Lumped RCs R p ∑ ∑ = × � t R C − df pulldown pulldown path � Elmore RC modeling C � Distributed RCs R n ∑ = � t R C d i i i Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51 Example � Consider a 4-input NAND as shown below � Simple RC model ∑ ∑ ∑ ∑ = × t R C − df f pulldown p pulldown p path p = + + + × + + + ( ) ( ) R R R R C C C C N 1 N 2 N 3 N 4 out ab bc cd = × t R C dr p 4 out P 4 P 3 P 2 P 1 out � Elmore RC model A N 4 C out C ab ∑ = t R C B N 3 d i i i C bc C = × + + × ( ) [( ) ] t R C R R C C N 2 1 1 2 df N cd N N bc + + + × C cd [( ) ] R R R C N 1 N 2 N 3 ab D N 1 + + + + × [( R R R R ) C ] N 1 N 2 N 3 N 4 out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52 26

Cascaded CMOS Inverter � As discussed above, if we want to have approximately the same rise and fall times for an inverter, for current CMOS process, we must m k make � W p =2-3W n � Increase layout area and dynamic power dissipation � In some cascaded structures it is possible to use minimum or equal-size devices without minimum or equal size devices without compromising the switching response � In the following, we illustrate two examples to explain why it is possible Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53 Cascaded CMOS Inverter � Example 1: = + t t t t inv-pair − inv pair fall rise R = + I h I charge R R 3 3 C C 2 2 3 3 C C 4/1 4/1 eq eq 2 R R = + 2/1 3C eq 3C eq 3 3 RC RC I discharge eq eq = W p =2W n 6 RC eq � Example 2: t inv-pair inv pair = + t t t − inv pair fall rise I charge 2/1 = + 2 2 2 2R R R C R C eq eq 2/1 2C eq 2C eq = 6 RC I discharge eq W p =W n Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54 27

Stage Ratio � To drive large capacitances such as long buses, I/O buffers, etc. � Using a chain of inverters where each successive inverter is made larger than the previous one until inverter is made larger than the previous one until the last inverter in the chain can drive the large load in the time required � The ratio by which each stage is increased in size is called stage ratio � Consider the circuit shown below � It consists of n-cascaded inverters with stage- ratio a driving a capacitance C L 1 a 2 a 3 a C L n(4) stages Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55 Stage Ratio � The delay through each stage is at d , where t d is the average delay of a minimum-sized inverter driving another minimum-sized inverter � Hence the delay through n stages is nat d � H th d l th h st s is t � If the ratio of the load capacitance to the capacitance of a minimum inverter, C L /C g , is R, then a n =R � Hence ln(R)=nln(a) � Thus the total delay is ln(R)(a/ln(a))t d � Thus the total delay is ln(R)(a/ln(a))t d � The optimal stage ratio may be determined from + k a opt C where k is drain = � a a e opt C opt gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56 28

Power Dissipation � Instantaneous power � The value of power consumed at any given instant = ( ) ( ) ( ) � P t v t i t � P � Peak power k � The highest power value at any given instant; peak power determines the component’s thermal and electrical limits and system packaging requirements = � P Vi peak peak � Average power � Average power � The total distribution of power over a time period; average power impacts the battery lifetime and heat dissipation 1 + + V � t T t T ∫ ∫ = = ( ) ( ) P P t dt i t dt ave T T t t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57 Power Analysis for CMOS Circuits � Two components of power consumption in a CMOS circuit � Static power dissipation � Caused by the leakage current and other static current d b h l k d h � Dynamic power dissipation � Caused by the total output capacitance � Caused by the short-circuit current � The total power consumption of a CMOS circuit is = + + � P P P P t s sw sc � P s : static power (leakage power); P sw : switching power; P sc : short-circuit power Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58 29

Static Power � Static dissipation is major contributed by � Reverse bias leakage between diffusion regions and the substrate � Subthreshold conduction V in Gnd V DD PN junction reverse bias V out leakage current p + n + p + n + n + p + = = − qV / KT ( ( 1 1 ) ) i i i i e e 0 s n-well n ∑ = × P I V sup s leakage ply p-substrate 1 n=number of devices Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59 Dynamic Power Dissipation � Switching power � Caused by charging and discharging the output capacitive load � Consider an inverter operated at a switching � C id i d i hi frequency f=1/T 1 ∫ T = ( ) ( ) P i t v t dt sw o o T 0 V DD dv = = o i i C i p p o L dt V out dv = = − = = − V in V in o i i i i C C n o L dt i o i n C L 1 ∫ V ∫ 0 = − DD [ ] P C v dv C v dv sw L o o L o o T 0 V DD 2 C V = = 2 L DD P fC V sw L DD T Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 60 30

Power & Energy � Energy consumption of an inverter (from ) → 0 V DD � The energy drawn from the power supply is = = � 2 2 E QV C L V DD � The energy stored in the load capacitance is = ∫ 1 � V = DD 2 E C v dv C V cap o o L DD 2 0 � The output from → 0 V DD � The E cap is consumed by the pull-down NMOS � Low-energy design is more important than low- power design � Minimize the product of power and delay Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 61 Short-Circuit Power Dissipation � Even if there were no load capacitance on the output of the inverter and the parasitics are negligible, the gate still dissipate switching energy � If the input changes slowly, both the NMOS and f h h l l b h h N d PMOS transistors are ON, an excess power is dissipated due to the short-circuit current � We are assuming that the rise time of the input is equal to the fall time � The short-circuit power is estimated as � The short circuit power is estimated as P = � I V sc mean DD Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 62 31

Short-Circuit Power Dissipation � I mean can be estimated as follows V in T V DD t r t f V DD |V tp | V DD -|V t | r f i sc V tn V in V out C L I max I mean t 1 t 2 t 3 1 ∫ t ∫ t = × 2 + 3 2 [ ( ) ( ) ] I i t dt i t dt mean T t t 1 2 4 ∫ t = 2 [ ( ) ] I i t dt mean T t 1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 63 Short-Circuit Power Dissipation � The NMOS transistor is operating in saturation, hence the above equation becomes β β 4 ∫ ∫ t = − 2 2 2 I I [ [ ( ( V V ( ( t t ) ) V V ) ) dt dt ] ] mean in T 2 T t 1 V = ( ) DD V t t in t r V = T t t 1 r V DD t = r t t 2 2 2 β = = τ = − τ 3 ( t t ) P ( V 2 V ) f r f sc DD T 12 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 64 32

Power Analysis for Complex Gates � The dynamic power for a complex gate cannot be estimated by the simple expression C L V DD f � Dynamic power dissipation in a complex gate � Internal cell power � Capacitive load power V DD � Capacitive load power B C = α 2 � P C V f L L DD C 1 � Internal cell power p A out n ∑ � = α A C P C V V f int i i i DD = i 1 B C 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65 Glitch Power Dissipation � In a static logic gate, the output or internal nodes can switch before the correct logic value is being stable. This phenomenon results in spurious transitions called glitches ABC 100 111 A D B D Z C Z Unit delay Spurious transition Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66 33

Rules for Avoiding Glitch Power � Balance delay paths; particularly on highly loaded nodes � Insert, if possible, buffers to equalize the fast path � Avoid if possible the cascaded design � Avoid if possible the cascaded design � Redesign the logic when the power due to the glitches is an important component Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 67 Principles for Power Reduction � Switching power dissipation = α 2 � P C V f L L DD n ∑ ∑ = α � P C V V f int i i i DD = i 1 � Prime choice: reduce voltage � Recent years have seen an acceleration in supply voltage reduction � Design at very low voltage still open question (0.6V…0.9V by 2010) � Reduce switching activity � Reduce physical capacitance Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 68 34

Layout Guidelines for LP Designs � Identify, in your circuit, the high switching nodes � Keep the wires of high activity nodes short � Use low-capacitance layers (e.g., metal2, metal 3, etc ) for high capacitive nodes and busses etc.) for high capacitive nodes and busses � Avoid, if possible, the use of dynamic logic design style � For any logic design, reduce the switching activity, by logic reordering and balanced delays through gate tree to avoid glitch problem � In non-critical paths, use minimum size devices � I iti l th i i i d i whenever it is possible without degrading the overall performance requirements � If pass-transistor logic style is used, careful design should be considered Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 69 Sizing Routing Conductors � Why do metal lines have to be sized? � Electromigration � Power supply noise and integrity (i.e., satisfactory power and signal voltage levels are presented to d i l lt l l t d t each gate) � RC delay � Electromigration is affected by � Current density � Temperature � Temperature � Crystal structure � For example, the limiting value for 1 um-thick aluminum is = 1 → μ 2 / J Al mA m Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 70 35

Power & Ground Bounce � An example of ground bounce Voltage V in L V out V DD Pad Time Current V out Time V in I I V SS Pad V SS Pad V L L V L =L(di/dt) Time Ground bounce Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 71 Approaches for Coping with L(di/dt) � Multiple power and ground pins � Restrict the number of I/O drivers connected to a single supply pins (reduce the di/dt per supply pin) � Careful selection of the position of the power and ground pins on the package � Avoid locating the power and ground pins at the corners of the package (reduce the L) � Increase the rise and fall times � Reduce the di/dt � Reduce the di/dt � Adding decoupling capacitances on the board � Separate the bonding-wire inductance from the inductance of the board interconnect Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 72 36

Contact Replication � Current tends to concentrate around the perimeter in a contact hole � This effect, called current crowding , puts a practical upper limit on the size of the contact ti l li it th i f th t t � When a contact or a via between different layers is necessary, make sure to maximize the contact perimeter (not area) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 73 Charge Sharing � Charge Q=CV � A bus example is illustrated to explain the charge sharing phenomenon � A bus can be modeled as a capacitor C b � An element attached to the bus can be modeled as a capacitor C s Bus V b C b V s C s Q = Q = ( ) ( ) C V C V b b b s s s Q = + = = + + Q C V C V V T ( C V C V ) /( C C ) T b b s s R b b s s b s C = + T C C C T b s Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 74 37

Design Margining � The operating condition of a chip is influenced by three major factors � Operating temperature � Supply voltage � S l lt � Process variation � One must aim to design a circuit that will reliably operate over all extremes of these three variables � Design corners � Design corners � Simulating circuits at all corners is needed � SS � TT � FF Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 75 Package Issues � Packaging requirements � Electrical: low parasitics � Mechanical: reliable and robust � Thermal: efficient heat removal h l ff h l � Economical: cheap � Bonding techniques Wire Bonding Substrate Substrate Die Pad Lead Frame Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 76 38