ECED2200 Digital Circuits Multiplexor & Demultiplexor - PowerPoint PPT Presentation

ECED2200 – Digital Circuits Multiplexor & Demultiplexor 18/07/2012 Colin O’Flynn - CC BY-SA 1

General Notes See updates to these slides: www.newae.com/teaching • These slides licensed under ‘Creative Commons Attribution-ShareAlike 3.0 • Unported License’ These slides are not the complete course – they are extended in-class • You will find the following references useful, see • www.newae.com/teaching for more information/links: The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the – class and you may have already 18/07/2012 Colin O’Flynn - CC BY-SA 2

Multiplexor/Demultiplexor 18/07/2012 Colin O’Flynn - CC BY-SA 3

What is a Multiplexor? 18/07/2012 Colin O’Flynn - CC BY-SA 4

2:1 Mux I 0 Q 0 I 1 2:1 Mux S 0 18/07/2012 Colin O’Flynn - CC BY-SA 5

4:1 Mux I 0 Q 0 I 1 4:1 Mux I 2 I 3 S 1 S 0 18/07/2012 Colin O’Flynn - CC BY-SA 6

Equations of Mux S1 S0 Q0 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 3 18/07/2012 Colin O’Flynn - CC BY-SA 7

8:1 Mux I 0 I 1 I 2 I 3 Q 0 8:1 Mux I 4 I 5 I 6 I 7 S 2 S 1 S 0 18/07/2012 Colin O’Flynn - CC BY-SA 8

Mux as Design Block A B C Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 18/07/2012 Colin O’Flynn - CC BY-SA 9

Mux as Design Block 0 I 0 A B C Y 1 I 1 0 0 0 0 0 I 2 0 0 1 1 Q 0 0 1 0 0 1 I 3 8:1 Mux 0 1 1 1 0 I 4 1 0 0 0 0 I 5 1 0 1 0 1 I 6 1 1 0 1 1 I 7 S 2 1 1 1 1 S 0 S 1 A B C 18/07/2012 Colin O’Flynn - CC BY-SA 10

Mux as a Design Block I 0 I 1 I 2 Y I 3 8:1 Mux I 4 I 5 I 6 I 7 S 2 S 0 S 1 A B C 18/07/2012 Colin O’Flynn - CC BY-SA 11

What is a Demultiplexor? 18/07/2012 Colin O’Flynn - CC BY-SA 12

2:4 Decoder / Demux D E Q 0 Q 0 Q 1 2:4 Q 1 2:4 Q 2 Q 2 Demux Decoder Q 3 Q 3 S 1 S 0 I 1 I 0 Inputs Address Select 18/07/2012 Colin O’Flynn - CC BY-SA 13

Notation Information • When using ‘Enable’ (tie to ‘1’), we have a decoder . When inputting data, we have demultiplexor (demux) . • Naming: – Decoder/demux named by “control signals:outputs” (e.g.: 2:4) – Mux named by “inputs:outputs” (e.g.: 4:1) 18/07/2012 Colin O’Flynn - CC BY-SA 14

Decoder as a Design Block E=‘1’ Q 0 Q 1 Q 2 3:8 Q 3 Q 4 Decoder Q 5 Q 6 Q 7 I 2 I 1 I 0 A B C 18/07/2012 Colin O’Flynn - CC BY-SA 15

Decoder as a Minterm Generator E=‘1’ Q 0 A•B•C Q 1 A•B•C Q 2 A•B•C 3:8 Q 3 A•B•C Q 4 Decoder A•B•C Q 5 A•B•C Q 6 A•B•C Q 7 A•B•C I 2 I 1 I 0 A B C 18/07/2012 Colin O’Flynn - CC BY-SA 16

TRI-STATE GATES 18/07/2012 Colin O’Flynn - CC BY-SA 17

Inverter 18/07/2012 Colin O’Flynn - CC BY-SA 18

3-State Buffer A E Q 0 1 0 1 1 1 0 0 Z 1 0 Z 18/07/2012 Colin O’Flynn - CC BY-SA 19

Uses for 3-State Buffers 18/07/2012 Colin O’Flynn - CC BY-SA 20

References See class notes “Beyond Simple Logic Gates” (page 133) 18/07/2012 Colin O’Flynn - CC BY-SA 21