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2. Design of Digital Circuits(S2) Chapter 1, Part 2 Modelling and Simulation Section 1.3 Delay Time Tolerance to 1.6 Sequential Circuits Prof. G. Kemnitz Institute of Informatics, Clausthal University of Technology May 14, 2012 Prof. G.

  1. 3. Delay Time Tolerance 3. Delay tolerance region G1:z1 < = ’X’ after th, x1 and x2 after td1; G2:z2 < = ’X’ after th, x3 and x4 after td1; G3: y < = ’X’ after th, z1 or z2 after td2; x 1 1 0 x 2 1 0 x 3 1 0 x 4 1 0 z 1 1 0 z 2 1 0 y 1 0 0 5 10 15 20 t sim not initialized (U) invalid (X) without t h the output signal is in the example most time invalid invalid means ≫ not necessary correct ≪ circuits processing invalid signal values may operate right, but reliable; difficult to debug Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 19/129

  2. 3. Delay Time Tolerance 4. Run Time Analysis Run Time Analysis Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 20/129

  3. 3. Delay Time Tolerance 4. Run Time Analysis Run Time Analysis Calculation of the hold and delay time of the complete circuit from the timing parameters of the subcircuits � t h .i � t d .i t d1 =2 ns path t d3 = 2 ns t h1 =1 ns t d5 = 2 ns t h3 =1 ns t h5 = 1 ns G1-G3-G5 3 ns 6 ns x 1 & x 2 & G1 G2-G3-G5 3 ns 7 ns & y 1 G3 t d2 =3 ns G5 t d4 =3 ns G2-G4-G5 3 ns 8 ns t h2 =1 ns t h4 =1 ns G2-G4 2 ns 6 ns x 3 & x 4 & y 2 G2 G4-G5 2 ns 5 ns G4 x 5 G4 1 ns 3 ns Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 21/129

  4. 3. Delay Time Tolerance 4. Run Time Analysis summing up the hold and delay times along the path’s the hold time of the complete circuit is that of the shortest path the delay time of the complete circuit is that of the path with the longest delay Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 22/129

  5. 3. Delay Time Tolerance 4. Run Time Analysis Algorithm for Large Circuits the number of path’s grows exponentially; better algorithm with linear order: repeat for each signal group starting from the inputs calculate hold and delay time to it t d1 =2 ns t d3 = 2 ns t h1 =1 ns t d5 = 2 ns t h3 =1 ns t h5 = 1 ns x 1 & x 2 & G1 & y 1 G3 t d2 =3 ns G5 t d4 =3 ns t h2 =1 ns t h4 =1 ns x 3 & x 4 & y 2 G2 G4 x 5 Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 23/129

  6. 3. Delay Time Tolerance 4. Run Time Analysis signal t hS .i t dS .i group 0 0 (Definition) 0 (Definition) t d . 1 t h . 1 1 t hS . 0 + t h . 1 t dS . 0 + t d . 1 t d . 2 t h . 2 2 t hS . 0 + t h . 2 t dS . 0 + t d . 2 3 min( t hS . 1 , t h . 2 ) max( t dS . 1 , t dS . 2 ) t d . 3 t h . 3 5 t hS . 3 + t h . 3 t dS . 3 + t d . 3 4 t hS . 0 t d . 2 t d . 4 t h . 4 6 t hS . 0 + t h . 4 t dS . 2 + t d . 4 7 min( t hS . 5 , t h . 6 ) max( t dS . 5 , T d . 6 ) t d . 5 t h . 5 8 t hS . 7 + t h . 5 t dS . 7 + t d . 5 9 min( t hS . 6 , t hS . 9 ) max( t dS . 6 , t dS . 9 ) linear order ⇒ also for large circuits Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 24/129

  7. 3. Delay Time Tolerance 5. Exercises Exercises Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 25/129

  8. 3. Delay Time Tolerance 5. Exercises Aufgabe 1.9: Hazard 2 ns x 0 1 G2 x 0 0 & x 1 1 z 1 1,5 ns 1 ns 0 G4 G1 z 0 x 2 1 4 ns 0 x 1 & y G3 0 2 4 6 8 10 == t sim x 2 z 2 VHDL description of the circuit with concurrent signal assignments VHDL description of the input assignments calculate the signal forms of z 1 , z 2 and y What signal transactions causes a glitch? Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 26/129

  9. 3. Delay Time Tolerance 5. Exercises Aufgabe 1.10: VHDL delay models signal y: STD LOGIC ; ... --- nebenl¨ aufige Zuweisungen y < = ’0’, ’X’ after 3 ns, ’1’ after 7 ns, ’X’ after 8 ns, ’1’ after 10 ns, ’0’ after 11 ns, ’1’ after 13 ns, ’1’ after 15 ns, ’X’ after 18 ns, ’0’ after 20 ns; wait for 5 ns; y < = ’1’ after 12 ns; --- y < = transport ’1’ after 12 ns; --- y < = reject 8 ns inertial ’1’ after 12 ns; With pending transactions are deleted, if the second assignment uses 1 the default delay model 2 the transport model 3 the inertial model with 8 ns reject time? Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 27/129

  10. 3. Delay Time Tolerance 5. Exercises Aufgabe 1.11: Run time analysis --- Vereinbarungsteil der Entwurfseinheit signal x: STD LOGIC VECTOR (4 downto 0):=”01011”; signal z: STD LOGIC VECTOR (4 downto 0); signal y: STD LOGIC ; --- Anweisungsteil der Entwurfseinheit G1: z(0) < = ’X’ after 4 ns, x(0) and x(1) after 8 ns; G2: z(1) < = ’X’ after 5 ns, x(2) or x(3) after 6 ns; G3: z(2) < = ’X’ after 3 ns, z(0) or z(1) after 6 ns; G4: z(3) < = ’X’ after 4 ns, z(1) and x(3) after 7 ns; G5: z(4) < = ’X’ after 3 ns, z(3) or x(4) after 5 ns; G6: y < = ’X’ after 5 ns, z(2) or z(4) after 7 ns; 1 Draw the signal flow plan with hold and delay times. 2 Calculate the hold and the delay time of the complete circuit. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 28/129

  11. 4. Register Register Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 29/129

  12. 4. Register Period of validity and sampling 1 t d1 t d2 t d3 t GE 0 0 z 3 & z 4 z 2 ≥ 1 z 1 1 z 1 ≥ 1 0 z 2 0 1 t h3 , t d3 t h2 , t d2 z 3 1 t h1 , t d1 0 z 4 1 0 t GA period of validity at the begin of the path t GE periode of validity at the end of the path t GA t h1 t h2 t h3 period of validity a the output: 3 3 � � t GA = t GE + t h i − t d i i =1 i =1 decreases with the length of the processing chain broadening of the period of validity ⇒ sampling (register) Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 30/129

  13. 4. Register 1. Sampling with Registers Sampling with Registers Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 31/129

  14. 4. Register 1. Sampling with Registers Sampling with Registers T t s t n t s t n t s , t n t hr , t dr w 1 w 2 x tTyp tTyp x ’ w 0 w 1 w 2 x x ’ t hr T t dr register: samples input data with the active clock edge 1 , else store t s set-up time, time input data must be stable before the active clock edge t n input hold time, time, the input data mus be stable after the active clock edge; will be often neglected t hr , t dr hold and delay time of the register tTyp: data type, ≫ STD LOGIC ≪ , vector type of is, ... 1 rising, falling edge or both Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 32/129

  15. 4. Register 1. Sampling with Registers Clock Signal T t s t n t s t n t s , t n t hr , t dr w 1 w 2 x tTyp tTyp x ’ w 0 w 1 w 2 x ’ x t hr T t dr Clocks are special signals, switching periodically between ≫ 0 ≪ and ≫ 1 ≪ and are used for time adjustment of data signal transitions modelled as ideal binary signals (without ≫ X ≪ ) the delay tolerance region is described by the register parameters clock signals must be exactly in time and glitch free; require special circuitry active clock edge: rising, falling, both Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 33/129

  16. 4. Register 1. Sampling with Registers Notation for sampled signals Sampling is a basic function of digital circuits; definition of a notation: the signal sampled by a signal x will be named x + (following state) (in VHDL x next) the sampled signal of x will be called x ’, the sampled signal of x ’ will be called x ” etc. (in VHDL x del, x del2 etc.) x + x x ’ x ” (x next) (x del) (x del2) T Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 34/129

  17. 4. Register 2. VHDL sampling process VHDL sampling process Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 35/129

  18. 4. Register 2. VHDL sampling process VHDL sampling process behaviour of a sampling process sampling process: process(T) begin if active clock edge then output signal < = invalid after th, input value after td; check input setup time check input hold time end if; end process; additional required description means: case distinction check for clock edges (signal attribute) instructions to control input setup and hold conditions Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 36/129

  19. 4. Register 2. VHDL sampling process signal attribute, description means to check additional signal features: signal s: tTyp; constant t: DELAY LENGTH ; s’ EVENT → BOOLEAN True, if the process has been waked-up by a transition of s s’ STABLE (t) → BOOLEAN True, true if there was no transition since time t s’ LAST EVENT → time since the last transition DELAY LENGTH s’ LAST VALUE → tTyp value before the last transition of s s’ DELAYED (t) → tTyp the by t delayed signal of s . . . Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 37/129

  20. 4. Register 2. VHDL sampling process functions to check, whether a process was awakened be an active edge (Package IEEE.STD LOGIC 1164 ): function RISING EDGE ( signal T: STD LOGIC ) return BOOLEAN is begin return T’ EVENT and T=’1’; end function ; function FALLING EDGE ( signal T: STD LOGIC ) return BOOLEAN is begin return T’ EVENT and T=’0’; end function ; control input setup and hold conditions: s’ STABLE (t); s’ LAST EVENT binary case distinction for control flow: if b then { sequential statement ;} end if; ( b – condition of type BOOLEAN , e.g. ≫ RISING EDGE (T) ≪ Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 38/129

  21. 4. Register 2. VHDL sampling process control instructions: assert b [report m ] [severity sl ]; ( m – additional message text; sl – severity level; data type: type SEVERITY LEVEL is ( NOTE , WARNING , ERROR , FAILURE ); Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 39/129

  22. 4. Register 2. VHDL sampling process t dr Simple register model tTyp tTyp x y signal T: STD LOGIC ; T signal x, y: tTyp; T constant tdr: DELAY LENGTH :=...; ... w 1 w 2 w 3 x process(T) y w 0 w 1 w 2 begin if RISING EDGE (T) then t d y < = x after tdr; end if; end process; process with only the clock in the sensitivity list output assignment only when a rising edge RISING EDGE (T) ⇒ ≫ T’ EVENT and T=’1’ ≪ ; if the process awakens ≫ T’ EVENT ≪ is ≫ TRUE ≪ ; except when the simulation starts Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 40/129

  23. 4. Register 2. VHDL sampling process A complete model t s , t n t hr , t dr tTyp tTyp process (T) x x ’ T begin if RISING EDGE (T) then T t s t n t s t n if x’ LAST EVENT > ts then w 1 w 2 x y < = invalid after thr, x after tdr; x ’ wait for tn; w 0 w 1 w 2 t hr if x’ LAST EVENT < tn then t dr y < = invalid ; signals: report "input hold cond. violated" T clock severity WARNING ; x input signal x ’ (x del) sampled end if ; (output) signal register parameter: else t s setup time y < = invalid after thr; t n input hold time report "setup cond. violated" t hr (output) hold time t dr delay time severity WARNING ; tTyp type data signal end if ; w i signal value end if ; sample window end process ; invalid Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 41/129

  24. 4. Register 2. VHDL sampling process No input hold time check ( t n = 0) and warnings process (T) begin if rising edge(T) then if x’last event > ts then y < = invalid after thr, x after tdr; else y < = invalid after thr; end if ; end if ; end process ; This will be the simulation model of a register generally use in the following. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 42/129

  25. 4. Register 3. Processing + Sampling Processing + Sampling Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 43/129

  26. 4. Register 3. Processing + Sampling Processing and sampling of the results t hf , t df t s t hr , t dr T t hf y + t df + t s f ( x ) x y x w i T t s y + required period f ( w i ) of validity t dr process (T) t hr begin f ( w i − 1 ) f ( w i ) y if RISING EDGE (T) then if x’ DELAYED (thf)’ LAST EVENT > tdf+ts-thf then y < = invalid (1) after thr, f(x) after tdr; else y < = invalid (1) after thr; end if ; end if ; end process ; (1) f¨ ur STD LOGIC ’X’; f¨ ur STD LOGIC VECTOR ”XX...X” Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 44/129

  27. 4. Register 3. Processing + Sampling Processing of sampled signals t s t hr , t dr t hf , t df T x ’ x w i f ( x ) x y t s t df t hf T x ’ w i − 1 w i process (T) t df begin t hf if RISING EDGE (T) then if x’ LAST EVENT > ts then y f ( w i − 1 ) f ( w i ) y < = invalid after thr+thf, f(x) after tdr+tdf; else y < = invalid after thr+thf; end if ; end if ; end process ; Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 45/129

  28. 4. Register 4. Register transfer function Register transfer function Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 46/129

  29. 4. Register 4. Register transfer function Register transfer function combinatorial function block framed by registers T P T P T t dr t dr t s , t n t hr , t dr t hr , t dr t hf , t df t s , t n t hr t hr w 0 w 1 w 2 x’ y = f ( x ) x y’ t df y x’ t hf t hf T t s t n y f ( w 0 ) f ( w 1 ) T P duration of the clock cycle x ’, y ’ sampled values, in the VHDL decription x del, y del Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 47/129

  30. 4. Register 4. Register transfer function T P T P T t dr t dr t s , t n t hr , t dr t hr , t dr t hf , t df t s , t n t hr t hr x’ w 0 w 1 w 2 x y = f ( x ) y’ t df y x’ t hf t hf T t s t n y f ( w 0 ) f ( w 1 ) T P duration of the clock cycle x ’, y ’ sampled values, in the VHDL decription x del, y del Requirements to sample valid output values T P ≥ T Pmin = t dr + t df + t s t n ≤ t nmax = t hr + t hf Both requirements can be checked with a run time analysis (befor simulation) Simulation model can be greatly simplified Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 48/129

  31. 4. Register 4. Register transfer function t hr , t dr t s , t n T P f ( ... ) x y’ y x’ T Processing: process(T): begin if RISING EDGE (T) then if x’ LAST EVENT > ts then x del < = x; else x < = invalid ; end if; y del < = invalid after th, f(x del) after td; end if; end process; Simplification to multiple processest undelayed assignment to x’ (x del) no check of setup conditions for y Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 49/129

  32. 4. Register 5. Clock skew Clock skew Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 50/129

  33. 4. Register 5. Clock skew Clock skew T P t ∆T12 t hr , t dr t hf , t df t s , t n T 1 x ′ y ′ y x f ( x ’) T 2 t hr t dr t ∆T12 x ′ T 2 T 1 delay t hf a) t df t s t n sampling edge of input register y sampling edge of output register 0 t b) sampling window Clock skew t ∆T12 : time offset between active clock edges between input and output registers intended to increase the max. clock frequency unintended by different delays Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 51/129

  34. 4. Register 5. Clock skew T P t ∆T12 t hr , t dr t hf , t df t s , t n T 1 x ′ y y ′ x f ( x ’) T 2 t hr t dr t ∆T12 x ′ T 2 T 1 delay t hf a) t df t s t n sampling edge of input register y sampling edge of output register 0 t b) sampling window Requirements for correct sampling: t dr + t df + t s ≤ T P + t ∆T12 t hr + t hf ≥ t n + t ∆T12 Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 52/129

  35. 4. Register 5. Clock skew Requirements for correct sampling: t dr + t df + t s ≤ T P + t ∆T12 t hr + t hf ≥ t n + t ∆T12 Maximum allowed clock skew: t ∆T12 ≤ t hr + t hf − t n Maximum allowed clock frequency: 1 f T ≤ t dr + t df + t s + − t n − ( t hr + t hf ) Reciprocal value of the difference of the sum of the delay, the input hold, the setup and the output hold time. Circuits with a large hold time may be clocked faster with an appropriate clock skew then without Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 53/129

  36. 4. Register 5. Clock skew Summary Calculation results must be sampled within their periods of vality by registers. Registers are discribed by sampling processes. In a sampling process only the clock is in the sensitivity list. Sampling with the active clock edge. Setup or input hold condition violations invalidate register data. The description of the the combinatirial circuit before or after the register may include in the sampling processes; simplify simulation. Framing by an input and an output register; timing condition check by run time analysis; highly simplified simulation model. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 54/129

  37. 4. Register 6. Exercises Exercises Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 55/129

  38. 4. Register 6. Exercises Aufgabe 1.12: Desciption by a sampling process t h1 , t d1 t hr , t dr T t s t h2 , t d2 t 1 t 2 x 0 y + =1 x 1 x 0 x 1 & y t 3 G1 t 4 G2 Reg x 2 T x 2 t 5 a) y + t 6 sampling window t 7 invalid y b) signal x0, x1, x2, y next, T, y: STD LOGIC ; Describe t 1 to t 7 as funcions of the values of t h .. , t d ... etc. Describe the whole circuit as a sampling process Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 56/129

  39. 4. Register 6. Exercises Aufgabe 1.13: Register transfer function t dr = 1 ns t d1 = 0 , 5 ns t d2 = n · 1 ns t d3 = 2 ns t s = 0,5 ns x y + x + 1 1 n n n n 0 n x n − 1 T Determin: maximum allowed clock frequency as a function of the bit width n ? maximum allowed clock frequency for n = 16? Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 57/129

  40. 4. Register 6. Exercises Aufgabe 1.14: Clock skew t hr = 0 ns t hf = 5 ns t n = 0 t dr = 1 ns t df = 11 ns t s = 2 ns y = f ( x ) x y clock 1 clock 2 In which interval of time the clock skew has to be, so that for a clock frequncy f Clk = 100 MHz the setup an the input hold conditions are met? Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 58/129

  41. 5. Asynchronous input Asynchronous input Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 59/129

  42. 5. Asynchronous input asynchronous: ≫ without synchronisation ≪ the time delay between input change and the active clock edge is a transactions is a uniformly distributed random variable in the range: t xT ∈ { 0 , T P } also asyncronous signals may only be evaluated within their periods of vality special circuit solutions and VHDL descriptions are required Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 60/129

  43. 5. Asynchronous input 1. Sampling a single bit Sampling a single bit Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 61/129

  44. 5. Asynchronous input 1. Sampling a single bit Sampling of binary input signals a single bit has, even if invalid during the sampling period, has the sampling value ≫ 0 ≪ or ≫ 1 ≪ ; sampled signals are free of glitches and stable during the clock period t xT T P t xT T t s t hr , t dr t s t s t s t s x x x ′ t dr t dr t dr t dr t hr t hr t hr t hr T x ’ Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 62/129

  45. 5. Asynchronous input 1. Sampling a single bit Design error: Processing of unsampled inputs T a ′ a x w 1 w 2 T a t h , t d t d t d t d t s t h t h t h a y f ( w 1 , 0) f ( w 1 , 1) f ( w 2 , 1) f ( .. ) y ′ x y t s y ′ f ( w 0 , 0) XX f ( w 2 , 1) T (processed) asynchronous inputs are withe a sertain probability invalid during the sample period the sampled value of ≫ invalid ≪ is a random value in a ′ ∈ { 0 , 1 } n , mostly wrong, often anallowed, unpredictable behaviour Workaround: additional bitwise sampling of the asyncronous input Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 63/129

  46. 5. Asynchronous input 2. Switch de-bouncing Switch de-bouncing Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 64/129

  47. 5. Asynchronous input 2. Switch de-bouncing De-bouncing of signals from switches and keys typ. 1 bit input element: mechanical switch or key Bouncing: multiple on and off by mechanical vibrations de-bouncing: sampling with a period larger than the bouncing time Edge detection: sampling twice, check for difference T circuit to detect falling edges t P x & y x ’ x ” t Pr x x ’ T x ” t Pr maximum bouncing time x ” x ’ 11 10 00 01 11 t P > t Pr sample period Take care, without unreliable sampling! Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 65/129

  48. 5. Asynchronous input 2. Switch de-bouncing t h , t d signal T, x, x del, x del2, y: STD LOGIC ; & y ’ y ... x (clock) x ’ x ” process (T) T begin if RISING EDGE (T) then if x=’1’ then x del < =’1’; else ’0’; end if ; x del2 < = x del; end if ; end process ; y < = ’X’ after th not x del and x del2 after td; Sampling x : ≫ ’1’ �→ ’1’, sonst �→ ’0’ ≪ (template for ≫ sampled value ∈ { 0 , 1 } combinatorial output, shortly invalid after each active clock edge; may be glitches to use y as a clock, sample again Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 66/129

  49. 5. Asynchronous input 3. Asynch. initialization Asynch. initialization Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 67/129

  50. 5. Asynchronous input 3. Asynch. initialization Register with initialization input signal x, y: tTyp; x x y signal T, I: STD LOGIC ; I I constant aw: tTyp:=...; T ... process (T, I) begin if I=’1’ then y < = aw; elsif RISING EDGE (T) then y < = x; end if ; end process ; register stage before initialization ”UU...U” (uninitialized/invalid) ≫ aw ≪ any valid value Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 68/129

  51. 5. Asynchronous input 3. Asynch. initialization Potential malfunction initialization pulse to short I 1 t hr , t dr t hf , t df t s 0 T 1 0 x x f () y ’ x w 1 w 2 y x ’ I I x ′ w 0 w 1 w 2 T ≪ T P Even if the input register is initialized correctly, duration ist to short, in witch the initial value is stable at the register output. So the subsequent register may sample an invalid signal. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 69/129

  52. 5. Asynchronous input 3. Asynch. initialization Register of master-slave flipflops: master takes over before the active clock edge slave takes over after the active clock edge I initialization of the slave deactivation of I deactivation of I at the in the slave phase end of the slave phase I 1 I 1 0 0 T 1 T 1 0 0 w 1 w 2 w 1 w 2 x x x ′ w 0 w 1 w 2 x ′ w 0 w 2 ≪ T P invalid instead of w 1 Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 70/129

  53. 5. Asynchronous input 3. Asynch. initialization Robust initialization power-on sampling reset circuit U V signal T, I, I POR, reset I Tast: STD LOGIC ; button ... ≥ 1 I I POR < = ’1’, ’0’ after 1 ms; T process(T) begin if RISING EDGE (T) then if I POR=’0’ or I Tast=’0’ then I < =’1’; else I < =’0’; end if; end if; end process; power-on reset: after applying voltage active for t POR ≈ R · C sampling to align to the active clock edge Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 71/129

  54. 5. Asynchronous input 4. Parallel interface Parallel interface Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 72/129

  55. 5. Asynchronous input 4. Parallel interface Asynchronous parallel interface the receiver of asynchronous parallel data need additional information about the period of validity, e.g. the clock of the transmitter in the example x should be valid from each edge of T x for a duration of t g t g T P x x ’ w 0 w 1 w 2 w 3 w 4 w 5 x T x ’ =1 G T x T x T x ” T T asynchronous input signal x x ’ w 0 w 1 w 2 w 3 w 4 w 5 T x send clock T x ’ T system clock T x ” x ’ sampled input signal G validation signal for x ’ G Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 73/129

  56. 5. Asynchronous input 4. Parallel interface t g T P x x ’ w 1 w 2 w 3 w 4 w 5 x w 0 T x ’ =1 G T x T x T x ” T T asynchronous input signal x x ’ w 0 w 1 w 2 w 3 w 4 w 5 T x send clock T x ’ T system clock T x ” x ’ sampled input signal G validation signal for x ’ G all input signals sampled with a period T P < t g the clock is sampled twice sampled data are valid if the sampled transmitter clock differs from the twice sampled Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 74/129

  57. 5. Asynchronous input 4. Parallel interface synchronization circuit x ’ x f ( ... ) G T x ’ =1 T x T signal T, Tx, Tx del, Tx del2, G: STD LOGIC ; signal x, y: STD LOGIC VECTOR (...); ... process (T) symbol begin if RISING EDGE (T) then SYNC y x y < = x; T x G if Tx=’1’ then tx del < = ’1’; else tx del < = ’0’; end if ; tx del2 < = Tx del; end if ; end process ; G < = Tx del xor Tx del2; Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 75/129

  58. 5. Asynchronous input 4. Parallel interface Summary sample asyncronous signals before processing in addion de-bounce signals from mechanical switches; sample period larger bouncing time sample asynchronous initialization signals asynchronous parallel input signals needs additional validity information; sampling by a synchronization circuit forgotten sampling causes non-recurring malfunctions; difficult to locate; reduced reliability Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 76/129

  59. 5. Asynchronous input 5. Exercises Exercises Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 77/129

  60. 5. Asynchronous input 5. Exercises Aufgabe 1.15: Adding up asynchronous input U V x 0 + adder x 1 U V power supply + · · · (signal value ’1’) x n − 1 ground T (signal value ’0’) Under which operational conditions the circuit may have non-recurring malfunctions? How the circuit has to be changed to work reliable? Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 78/129

  61. 5. Asynchronous input 5. Exercises Aufgabe 1.16: Asynchronous parallel transmission During an asynchronous transmission data signal x should be valid if the also transmitted validity signal g is g � = 0: t g0 min. time g = 0 x w i w i +1 t g1 min. time g = 1 g 1 0 t g1 t g0 t gx max. time g = X t gx T Pg periodic time of g T Pg What clock frequency is required in the receiver circuit to sample x and g 2 ? How the validity signal in the receiver has to be generated, so that it is exactly valid for one receiver clock for each sampled data word? 2 Duration of g = 0 and g = 1 should be equal. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 79/129

  62. 5. Asynchronous input 5. Exercises Aufgabe 1.17: Hand clock Design a circuit with an input button x , en input clock T ( f T = 50 MHz) and internal clock divider to produce a de-bounced hand clock without glitches: entity HandClock is port (x: in std logic; -- input signal from button T: in std logic; -- input clock, 50MHz Tout: out std logic); -- hand clock, de-bounced, no glitches end entity ; Maximum bouncing time 20 ms Minimum activation time 100 ms. Divider proportion for the clock should be a power of two. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 80/129

  63. 5. Asynchronous input 5. Exercises 1 What is the advantage of a power of two for the divider proportion? (Note, the circuit has no initialization input.) 2 What values are allowed for the divider proportion? 3 Draw the whole circuit with the clock divider as a black box. 4 Describe the complete circuit in VHDL. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 81/129

  64. 6. Sequential circuit Sequential circuit Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 82/129

  65. 6. Sequential circuit Sequential circuit t h , t d I 1 0 1 T 0 f s ( x, s ) x s x X 0 X 1 X 2 x I I x + t d y I + f y ( x, s ) y ’ t h s + T S 0 S 1 S 2 state register s S 0 S 1 optinal input and output register combinatorial circuit y Y 0 Y 1 Y 2 point of sample time y ’ Y 0 Y 1 value valid sequential: in consecutive steps Calculation of the circuit outputs in multiple time steps combinatorial circuit + registers for sampling and storing Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 83/129

  66. 6. Sequential circuit 1. Finite state machine Finite state machine Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 84/129

  67. 6. Sequential circuit 1. Finite state machine Finite state machine general function model to describe sequential operations; defining value ranges as symbol sets: range of input values: Σ = { E 1 , E 2 , . . . } range of states: S = { Z 1 , Z 2 , . . . } (one is initial state) range of output values: Π = { A 1 , A 2 , . . . } and operation as mappings: transfer function: f s : S × Σ → S output function: f a : S × Σ → Π Digital circuits as finite state machines: symbols �→ bit vectors; input, output �→ signals state �→ register; transfer and output function �→ combinatorial circuit state transition synchronized to a clock initial state = initialing value of the state register Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 85/129

  68. 6. Sequential circuit 1. Finite state machine Description by a state graph E 1 . 1 E 2 . 1 symbol for the Z 1 A K1 . 1 Z 2 A K2 . 1 inital state A Z1 A Z2 transition condition E 1 . 2 E 2 . 2 state transition A K2 . 1 A K2 . 2 name of the state Z 3 state A Z2 E 3 . 1 output A K3 . 1 output depends only upon the state / assigned to states / the same for all outgoing edges �→ Moore automaton output also depends on input / assigned to the outgoing edges �→ Mealy automaton Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 86/129

  69. 6. Sequential circuit 1. Finite state machine Up-/down counter as a Mealy automaton H/K H/L s state V/L input value A B x/y output value R/K V/K R/N R/L V/M Σ = { H, V, R } range of input values R/M S = { A, B, C, D } range of state values D C Π = { K, L, M, N } range of output values V/N initial state H/N H/M Meanings of the input values: H – stop; V – up; R – down Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 87/129

  70. 6. Sequential circuit 1. Finite state machine state transition and output state state transition and output ⇒ ⇒ function with symbolic values coding function with bitvectors s + = f s ( x , s ) s + = f s ( x , s ) y = f a ( x , s ) y = f a ( x , s ) C 10 D 11 s x : V H R V H R V 0 0 s x : 00 01 10 00 01 10 H 01 A B A D L K N 00 01 00 11 01 00 11 K 00 R 10 B C B A M L K 01 10 01 00 10 01 00 L 0 1 C D C B N M L 10 11 10 01 11 10 01 A 00 M 10 D A D C K N M 11 00 11 10 00 11 10 B 0 1 N 11 state graph: obviously well suited to specify target functions extractable tabular state transfer and output function state coding: assigning bit vectors to symbols translation to a presentation with bit vectors Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 88/129

  71. 6. Sequential circuit 1. Finite state machine Up-/down counter as a Moore automaton s + = f s ( x , s ) a H H b y = f y ( s ) s state s x : V H R y output value V A B A B A D K x input value K L B C B A L R V R V R C D C B M x input R D A D C N actual state s D C s + next state N M { H, V, R } input set output y V { A, B, C, D } state set f s ( ... ) transfer function H H { K, L, M, N } output set f a ( ... ) output function the output depends on the state Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 89/129

  72. 6. Sequential circuit 1. Finite state machine Autonomous automaton no input; one outgoing edge per state A B C D A B C D H G F E E F G H a) b) a) cyclical automaton; example application clock divider b) without cycle but a final state; example initialization run If no outputs are assigned in the state graph the state is the output. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 90/129

  73. 6. Sequential circuit 2. Automaton ⇒ VHDL Automaton ⇒ VHDL Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 91/129

  74. 6. Sequential circuit 2. Automaton ⇒ VHDL Circuit structure of automatons t h , t d I 1 0 1 T 0 f s ( x, s ) x s x X 0 X 1 X 2 x I I x + t d y I + f y ( x, s ) y ’ t h s + T S 0 S 1 S 2 state register s S 0 S 1 optinal input and output register combinatorial circuit y Y 0 Y 1 Y 2 point of sample time y ’ Y 0 Y 1 value valid the input and the initialization signal must be aligned to the clock Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 92/129

  75. 6. Sequential circuit 2. Automaton ⇒ VHDL t h , t d f s ( x, s ) x s x I I x + y I + f y ( x, s ) y ’ T the optional input and output register are generally not counted as part of the automaton initializing the state register ⇒ switching to the initial state state register + transfer function ⇒ sampling process with initialization ( T , I in the sensitivity list) output function without sampling ⇒ combinatorial process ( x , s in the sensitivity list) Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 93/129

  76. 6. Sequential circuit 2. Automaton ⇒ VHDL VHDL case instruction to describe tabular functions else case expression is s s { | Wert } = > w 0 w 0 w 1 . . . when value { instruction } A 0 instruction . . . A 0 A 1 A n { when Wert { | Wert } = > w 1 { instruction }} A1 instruction [ [ when others = > s value to select { } ] ] A n w i values to bee selected i instruction instruction ; A i instruction sequence i end case the transfer an the output functions derived from the state graph best be described by case and if statements, e.g.: case state is when Z i = > if input=... then state < = Z j ; ... Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 94/129

  77. 6. Sequential circuit 2. Automaton ⇒ VHDL Example of a mealy automaton state graph circuit structure 0/1 f y y s + s 1/1 0/0 00 1/0 x f s x 0/0 I I 10 01 1/1 T T necessary, but not part of the automaton input range: { 0 , 1 } ⇒ bit Range oft states: { 00 , 01 , 10 } ⇒ 2 bit vector output range: { 0 , 1 } ⇒ bit signal x, y, T, I: STD LOGIC ; signal s: STD LOGIC VECTOR (1 downto 0); Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 95/129

  78. 6. Sequential circuit 2. Automaton ⇒ VHDL Transfer function in a sample process process (I, T) variable sx: STD LOGIC VECTOR (2 downto 0); begin 0/1 if I=’1’ then 0/0 1/1 00 1/0 0/0 s < = "00"; 10 1/1 01 elsif RISING EDGE (T) then sx := s & x; case sx is when "00"&’0’ | "10"&’0’ = > s < = "00"; when "01"&’0’ | "00"&’1’ = > s < = "01"; when "10"&’1’ | "01"&’1’ = > s < = "10"; when others = > s < = "XX"; end case ; s + end if ; f s x x s end process ; I I Selection expression: concatenation of state and input T Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 96/129

  79. 6. Sequential circuit 2. Automaton ⇒ VHDL Output function as combinatorial process 0/1 1/1 0/0 00 1/0 0/0 10 1/1 01 process (x, s) variable sx: STD LOGIC VECTOR (2 downto 0); begin sx < = s & x; case sx is when "00"&’1’ | "01"&’0’ | "10"&’0’ = > y < = ’0’; when "00"&’0’ | "01"&’1’ | "10"&’1’ = > y < = ’1’; when others = > y < = ’X’; end case ; end process ; The selection expression is again a concatenation of the state and the input. Prof. G. Kemnitz · Institute of Informatics, Clausthal University of Technology May 14, 2012 97/129

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