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ECED2200 Digital Circuits Time Response & Hazards 18/07/2012 - PowerPoint PPT Presentation

ECED2200 Digital Circuits Time Response & Hazards 18/07/2012 Colin OFlynn - CC BY-SA 1 General Notes See updates to these slides: www.newae.com/teaching These slides licensed under Creative Commons


  1. ECED2200 – Digital Circuits Time Response & Hazards 18/07/2012 Colin O’Flynn - CC BY-SA 1

  2. General Notes • See updates to these slides: www.newae.com/teaching • These slides licensed under ‘ Creative Commons Attribution-ShareAlike 3.0 Unported License ’ • These slides are not the complete course – they are extended in-class • You will find the following references useful, see www.newae.com/teaching for more information/links: – The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the class and you may have already 18/07/2012 Colin O’Flynn - CC BY-SA 2

  3. Time Response of Gates 18/07/2012 Colin O’Flynn - CC BY-SA 3

  4. NOT Gate Y=A A Y 0 1 1 0 18/07/2012 Colin O’Flynn - CC BY-SA 4

  5. NOT Gate Y=A A Y 0 1 1 0 18/07/2012 Colin O’Flynn - CC BY-SA 5

  6. Time Response Source: http://www.nxp.com/documents/data_sheet/74HC_HCT00.pdf 18/07/2012 Colin O’Flynn - CC BY-SA 6

  7. Typical Values 74F00: 74HC00: 74LS00: 18/07/2012 Colin O’Flynn - CC BY-SA 7

  8. USEFUL GATE DELAYS 18/07/2012 Colin O’Flynn - CC BY-SA 8

  9. Pulse Shaper A B C D Y 18/07/2012 Colin O’Flynn - CC BY-SA 9

  10. Ring Oscillator A B C D Y 18/07/2012 Colin O’Flynn - CC BY-SA 10

  11. NOT-SO-USEFUL GATE DELAYS 18/07/2012 Colin O’Flynn - CC BY-SA 11

  12. Glitches 18/07/2012 Colin O’Flynn - CC BY-SA 12

  13. Hazards • Circuits with potential for a glitch have a hazard 18/07/2012 Colin O’Flynn - CC BY-SA 13

  14. Types of Hazards Static 1-Hazard Static 0-Hazard Dynamic Hazard 18/07/2012 Colin O’Flynn - CC BY-SA 14

  15. What Creates Hazards? • Single-bit (variable) input changes only! 18/07/2012 Colin O’Flynn - CC BY-SA 15

  16. Analyzing Hazards & Fixing Them f    A B+B C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C 18/07/2012 Colin O’Flynn - CC BY-SA 16

  17. Hazard Free Form 18/07/2012 Colin O’Flynn - CC BY-SA 17

  18. Other Hazards? In two-level networks (assuming complements are available) synthesized in sum-of-product form, removal of state 1-hazard means static 0- hazards and dynamic hazards also removed. 18/07/2012 Colin O’Flynn - CC BY-SA 18

  19. Multilevel Hazards 1. Simplify using some basic Boolean laws to get to two-level form – CANNOT use complement laws or simplification laws derived from it 2. Using K-Map derive hazard-free form 3. Do not convert back into multilevel form – difficult to remove dynamic hazards 18/07/2012 Colin O’Flynn - CC BY-SA 19

  20. Example f=A•B•C+(A+D)•(A+C) f=A•B•C+A•A+A•C+D•A+D•C 18/07/2012 Colin O’Flynn - CC BY-SA 20

  21. Example f=A•B•C+A•A+A•C+D•A+D•C A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D 18/07/2012 Colin O’Flynn - CC BY-SA 21

  22. References See class notes “Hazards” 18/07/2012 Colin O’Flynn - CC BY-SA 22

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