CSE 140 Lecture 13 Standard Combinational Modules CK Cheng CSE - PowerPoint PPT Presentation

CSE 140 Lecture 13 Standard Combinational Modules CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1

Part III. Standard Modules Interconnect Operators. Representation of numbers Adders 1. Full Adder 2. Half Adder 3. Ripple-Carry Adder 4. Carry Look Ahead Adder 5. Prefix Adder ALU Comparator Shifter Multiplier Division 2

Design Flow • Specification: Data Representations • Arithmetic: Algorithms • Logic: Synthesis • Layout: Placement and Routing 3

1. Representation of numbers Negative Numbers • 2’s complement of n-bit vector -x: 2 n -x • 1’s complement of n-bit vector -x: 2 n -x-1 4

1. Representation Id 2’s 1’s • 2’s Complement comp. comp. 0 0 15 -x: 2 n -x -1 15 14 e.g. 16-x -2 14 13 • 1’s Complement -3 13 12 -x: 2 n -x-1 -4 12 11 e.g. 16-x-1 -5 11 10 -6 10 9 -7 9 8 -8 8 5

1. Representation Id -Binary sign mag 2’s comp 1’s comp 0 0000 1000 0000 1111 -1 0001 1001 1111 1110 -2 0010 1010 1110 1101 -3 0011 1011 1101 1100 -4 0100 1100 1100 1011 -5 0101 1101 1011 1010 -6 0110 1110 1010 1001 -7 0111 1111 1001 1000 -8 1000 6

Representation 1’s Complement For a negative number, we take the positive number and complement every bit. 2’s Complement For a negative number, we do 1’s complement and plus one. (b n-1 , b n-2 , …, b 0 ): -b n-1 2 n-1 + sum i<n-1 b i 2 i b n-1 =1 iff the number is negative 7

Representation 2’s Complement 1’s Complement • x+y • x+y • x-y: x+2 n -y= 2 n +x-y • x-y: x+2 n -y-1= 2 n -1+x-y • -x+y: 2 n -x+y • -x+y: 2 n -x-1+y=2 n -1-x+y • -x-y: 2 n -x+2 n -y • -x-y: 2 n -x-1+2 n -y-1 = 2 n +2 n -x-y = 2 n -1+2 n -x-y-1 • -(-x)=2 n -(2 n -x)=x • -(-x)=2 n -(2 n -x-1) -1=x 8

Examples 2 - 3 = -1 (2’s) 2 - 3 = -1 (1’s) 2 + 3 = 5 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 + 1 1 0 1 + 1 1 0 0 + 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 Check for overflow (2’s) -3 + -5 = -8 3 + 5 = 8 -2 - 3 = -5 (1’s) -2 - 3 = -5 (2’s) 1 1 1 1 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1 0 + 1 0 1 1 + 0 1 0 1 + 1 1 0 0 + 1 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 1 C 4 C 3 C 4 C 3 1 1 0 1 0 9

Addition: 2’s Complement Overflow In 2’s complement: overflow = c n ⊕ c n-1 Exercise: 1.Demonstrate the overflow with more examples. 2.Prove the condition. 10

Addition and Subtraction using 2’s Complement b b’ a C 4 D 0 D 1 overflow minus s 0 MUX C 3 Adder C in C out Sum 11

1-Bit Adders Half Full Adder Adder A B A B C out C out C in + + S S C out S A B C in A B C out S 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1 0 0 0 1 S = A ⊕ B 1 0 1 1 0 1 1 0 1 0 C out = AB 1 1 1 1 1 S = A ⊕ B ⊕ C in C out = AB + AC in + BC in 12

Half Adder a b S um = ab’ + a’b = a + b C out = ab HA S um C out a C out b a b C out S um 0 0 0 0 0 1 0 1 S um 1 0 0 1 1 1 1 0 13

Full Adder Composed of Half Adders x c out a c out OR HA sum b z y c out HA sum sum c in 14

Full Adder Composed of Half Adders a c out x HA c out b sum y z c out HA c in sum sum Id a b c in x y z c out s um Id x z c out 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 2 0 1 0 0 1 0 0 1 3 0 1 1 0 1 1 1 0 2 1 0 1 4 1 0 0 0 1 0 0 1 3 1 1 - 5 1 0 1 0 1 1 1 0 6 1 1 0 1 0 0 1 0 7 1 1 1 1 0 0 1 1 15

Adder • Several types of carry propagate adders (CPAs) are: – Ripple-carry adders (slow) – Carry-lookahead adders (fast) – Prefix adders (faster) • Carry-lookahead and prefix adders are faster for large adders but require more hardware. Symbol A B N N C out C in + N S 16

Ripple-Carry Adder • Chain 1-bit adders together • Carry ripples through entire chain • Disadvantage: slow A 31 B 31 A 30 B 30 A 1 B 1 A 0 B 0 C out C in + + + + C 31 C 30 C 2 C 1 S 31 S 30 S 1 S 0 17

Ripple-Carry Adder Delay • The delay of an N -bit ripple-carry adder is: t ripple = Nt FA where t FA is the delay of a full adder 18

Carry-Lookahead Adder • Compress the logic levels of C out • Some definitions: – Generate ( G i ) and propagate ( P i ) signals for each column: • A column will generate a carry out if A i AND B i are both 1. G i = A i B i • A column will propagate a carry in to the carry out if A i OR B i is 1. P i = A i + B i • The carry out of a column ( C i ) is: C i+1 = A i B i + ( A i + B i ) C i = G i + P i C i 19

Carry Look Ahead Adder C 1 = a 0 b 0 + (a 0 +b 0 )c 0 = g 0 + p 0 c 0 C 2 = a 1 b 1 + (a 1 +b 1 )c 1 = g 1 + p 1 c 1 = g 1 + p 1 g 0 + p 1 p 0 c 0 C 3 = a 2 b 2 + (a 2 +b 2 )c 2 = g 2 + p 2 c 2 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 C 4 = a 3 b 3 + (a 3 +b 3 )c 3 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0 q i = a i b i p i = a i + b i a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 g 3 p 3 g 2 p 2 g 1 p 1 g 0 p 0 c 0 c 4 c 3 c 2 c 1 20

Carry-Lookahead Addition • Step 1: compute generate ( G ) and propagate ( P ) signals for columns (single bits) • Step 2: compute G and P for k -bit blocks • Step 3: C in propagates through each k -bit propagate/generate block 21

32-bit CLA with 4-bit blocks B 31:28 A 31:28 B 27:24 A 27:24 B 7:4 A 7:4 B 3:0 A 3:0 C 28 C 24 C 4 C 8 4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA C out C in Block Block Block Block S 31:28 S 27:24 S 7:4 S 3:0 B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 3 C 2 C 1 C in + + + + S 3 S 2 S 1 S 0 G 3:0 G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 3 P 3:0 C out P 2 P 1 C in P 0 22

Carry-Lookahead Adder Delay • Delay of an N -bit carry-lookahead adder with k -bit blocks: t CLA = t pg + t pg_ block + ( N/k – 1) t AND_OR + kt FA where – t pg : delay of the column generate and propagate gates – t pg_ block : delay of the block generate and propagate gates – t AND _ OR : delay from C in to C out of the final AND/OR gate in the k -bit CLA block • An N -bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16 23

Prefix Adder • Computes the carry in ( C i -1 ) for each of the columns as fast as possible and then computes the sum: S i = ( A i ⊕ B i ) ⊕ C i • Computes G and P for 1-bit, then 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the carry in (generate signal) is known for each column • Has log 2 N stages 24

Prefix Adder • A carry in is produced by being either generated in a column or propagated from a previous column. • Define column -1 to hold C in , so G -1 = C in , P -1 = 0 • Then, the carry in to col. i = the carry out of col. i-1 : C i -1 = G i -1:-1 G i -1:-1 is the generate signal spanning columns i -1 to -1. There will be a carry out of column i -1 ( C i -1 ) if the block spanning columns i -1 through -1 generates a carry. • Thus, we rewrite the sum equation: S i = ( A i ⊕ B i ) ⊕ G i -1:-1 • Goal: Compute G 0:-1 , G 1:-1 , G 2:-1 , G 3:-1 , G 4:-1 , G 5:-1 , … (These are called the prefixes) 25

Prefix Adder • The generate and propagate signals for a block spanning bits i : j are: G i:j = G i:k + P i:k G k -1: j P i:j = P i : k P k -1:j • In words, these prefixes describe that: – A block will generate a carry if the upper part ( i : k ) generates a carry or if the upper part propagates a carry generated in the lower part ( k -1: j ) – A block will propagate a carry if both the upper and lower parts propagate the carry. 26

Prefix Adder Schematic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 14:13 12:11 10:9 8:7 6:5 4:3 2:1 0:-1 14:11 13:11 10:7 9:7 6:3 5:3 2:-1 1:-1 14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1 14:-1 13:-1 12:-1 11:-1 10:-1 9:-1 8:-1 7:-1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Legend i i i:j A i B i P i:k P k-1:j G i:k G k-1:j G i-1:-1 A i B i P i:i G i:i P i:j G i:j 27 S i

Prefix Adder Delay • The delay of an N -bit prefix adder is: t PA = t pg + log 2 N(t pg_ prefix ) + t XOR where – t pg is the delay of the column generate and propagate gates (AND or OR gate) – t pg_ prefix is the delay of the black prefix cell (AND-OR gate) 28

Adder Delay Comparisons • Compare the delay of 32-bit ripple-carry, carry- lookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is 100 ps and the full adder delay is 300 ps. 29

Adder Delay Comparisons • Compare the delay of 32-bit ripple-carry, carry- lookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is 100 ps and the full adder delay is 300 ps. t ripple = Nt FA = 32(300 ps) = 9.6 ns t CLA = t pg + t pg_ block + ( N/k – 1) t AND_OR + kt FA = [100 + 600 + (7)200 + 4(300)] ps = 3.3 ns t PA = t pg + log 2 N(t pg_ prefix ) + t XOR = [100 + log 2 32(200) + 100] ps = 1.2 ns 30

Comparator: Equality Symbol Implementation A 3 B 3 A 2 A B 4 4 B 2 Equal = A 1 B 1 Equal A 0 B 0 31

Comparator: Less Than • Compare two numbers A B N N - N [N-1] A < B 32