CSE 140 Lecture 11 Standard Combinational Modules CK Cheng CSE - PowerPoint PPT Presentation

CSE 140 Lecture 11 Standard Combinational Modules CK Cheng CSE Dept. UC San Diego 1

Part III - Standard Combinational Modules •Introduction •Decoder – Behavior, Logic, Usage •Encoder •Multiplexer (Mux) – Behavior, Logic, Usage •Demultiplexier (DeMux) 2

Part III - Standard Combinational Modules Signal Transport •Decoder: Decode address •Encoder: Encode address •Multiplexer (Mux): Select data by address •Demultiplexier (DeMux): Direct data by address •Shifter: Shift bit location Data Operator •Adder: Add two binary numbers •Multiplier: Multiply two binary numbers 3

Interconnect: Decoder, Encoder, Mux, DeMux Processors Arbiter Data 1 Mux Memory Bank P1 Data Address 1 P2 Demux n-m Address 2 Mux Address m 2 m n Address k Decoder Data k Decoder: Decode the address to assert the Pk addressed device Mux: Select the inputs according to the index addressed by the control signals 4

1. Decoder • Definition • Logic Diagram • Application (Universal Set) • Tree of Decoders 5

iClicker: Decoder Definition A. A device that decodes B. An electronic device that converts signals from one form to another C. A machine that converts a coded text into ordinary language D. A device or program that translates encoded data into its original format E. All of the above 6

Decoder Definition: A digital module that converts a binary address to the assertion of the addressed device E (enable) y 0 0 I 0 0 y 1 1 2 . 1 I 1 3 . 4 5 I 2 2 6 y 7 7 n to 2 n decoder 2 n outputs n inputs function: 2 3 = 8 n= 3 y i = 1 if E= 1 & (I 2, I 1, I 0 ) = i y i = 0 otherwise 7

1. Decoder: Definition • N inputs, 2 N outputs • One-hot outputs: only one output HIGH at most E 2:4 Decoder 11 Y 3 A 1 10 Y 2 A 0 01 Y 1 00 Y 0 E= 1 A 1 A 0 Y 3 Y 2 Y 1 Y 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 8

1. Decoder: Definition iClicker: A 3-input decoder has how many outputs? E A. 2 outputs B. 4 outputs C. 8 outputs D. 10 outputs 9

Decoder Definition iClicker: For a 3-input E (enable) decoder, suppose y 0 0 (E,I 2 ,I 1 ,I 0 )=(1,0,0,0), I 0 0 y 1 1 2 . 1 I 1 3 then (y 7 ,y 6 , …, y 0 ) is . 4 5 I 2 2 6 equal to: y 7 7 8 outputs A. (00000000) 3 inputs B. (00000001) C. (00000010) D. (01000000) E. (10000000) 10

Decoder: Logic Diagram (Inside a decoder) y 0 = 1 if (A 1, A 0 ) = (0,0) & En = 1 En y i = m i En 2:4 Decoder A 0 ’ 11 Y 3 A 1 ’ y 0 A 1 10 Y 2 A 0 01 Y 1 00 Y 0 y 1 . A 1 A 0 Y 3 Y 2 Y 1 Y 0 . 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 y 3 1 1 1 0 0 0 y 3 = A 1 A 0 En 11

1. Decoder: Definition PI Q: What is the output Y 3:0 of the 2:4 decoder for (A 1 , A 0 ) = (1,0)? 2:4 Decoder A. (1, 1, 0, 0 ) 11 Y 3 A 1 10 Y 2 B. (1, 0, 1, 1) A 0 01 Y 1 C. (0, 0, 1, 0) 00 Y 0 D. (0, 1, 0, 0) 12

Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 3-input decoder and OR gates. i) f 1 (a,b,c) = Σm(1,2,4) ii) f 2 (a,b,c) = Σm(2,3), iii) f 3 (a,b,c) = Σm(0,5,6) 13

Decoder Application: universal set {Decoder, OR} Decoder produces minterms when E=1. We can use an OR gate to collect the minterms to cover the On-set. For the Don’t Care-Set, we can just ignore the terms. 14

Decoder Application: universal set {Decoder, OR} Example: Implement functions i)f 1 (a,b,c) = Σm (1,2,4) + Σd (0,5), ii)f 2 (a,b,c) = Σm (2,3) + Σd (1,4), iii)f 3 (a,b,c) = Σm (0,5,6) y 1 y 2 with a 3-input decoder and OR gates. y 4 f 1 y 2 E=1 y 3 f 2 y 0 0 I 0 c 1 . 2 y 0 I 1 3 b . 4 y 5 5 I 2 a 6 y 7 7 y 6 f 3 15

Decoders • OR minterms E=1 2:4 Decoder Minterm 11 AB A 10 AB B 01 AB 00 AB Y = AB + AB = A ⊕ B Y 16

Tree of Decoders: Scale up the size of the decoders using a tree structure Implement a 4-2 4 decoder with 3-2 3 decoders. y 0 0 d I 0 . 1 2 I 1 c 3 4 5 I 2 b 6 y 7 7 y 8 0 I 0 1 . 2 I 1 3 4 5 I 2 6 y 15 7 a 17

Tree of Decoders Implement a 6-2 6 decoder with 3-2 3 decoders. E y 0 E I 2, I 1, I 0 D 0 y 7 y 8 I 5, I 4, I 3 I 2, I 1, I 0 D 1 y 15 … … y 56 I 2, I 1, I 0 D 7 y 63 18

PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following? A. 1:2 decoders and OR gates B. 2:4 decoders and OR gates C. 3:8 decoders and OR gates D. All of the above E. None of the above 19

2. Encoder • Definition • Logic Diagram • Priority Encoder 20

iClicker: Definition of Encoder A. Any program, circuit or algorithm which encodes B. In digital audio technology, an encoder is a program that converts an audio WAV file into an MP3 file C. A device that convert a message from plain text into code D. A circuit that is used to convert between digital video and analog video E. All of the above 21

Encoder Definition: A digital module that converts the assertion of a device to the binary address of the device. E I 2n-1… I 0 y n-1 … y 0 Encoder Description: A E At most one I i = 1. (y n-1 ,.., y 0 ) = i if I i = 1 & Ε = 1 I 0 0 y 0 0 1 2 y 1 (y n-1 ,.., y 0 ) = 0 otherwise. 1 3 4 2 y 2 A = 1 if E = 1 and one i s.t. I i = 1 5 6 I 7 7 A = 0 otherwise. 3 outputs A 8 inputs 22

Encoder: Logic Diagram En En y 0 y 1 I 2 I 1 I 3 I 3 I 5 I 6 I 7 I 7 En En y 2 I 4 A I 0 I 5 I 1 . I 6 . I 7 I 6 I 7 23

Priority Encoder: E I 0 0 y 0 0 1 2 y 1 3 1 I 3 Eo Gs 24

Priority Encoder: Definition Description: Input (I 2n-1 ,…, I 0 ), Output (y n-1 ,…, , y 0 ) (y n-1 ,…, , y 0 ) = i if I i = 1 & E = 1 & I k = 0 for all k > i (high bit priority) or E for all k< i (low bit priority) . E o = 1 if E = 1 & I i = 0 for all i, I 0 0 y 0 G s = 1 if E = 1 & i s.t. I i = 1 . E 0 1 2 1 y 1 3 (G s is like A, and E o passes on 4 2 5 y 2 6 enable). 7 I 7 Eo Gs 25

Priority Encoder: Implement a 32-input priority encoder w/ 8 input priority encoders (high bit priority). E I 31-24 y 32, y 31, y 30 Gs Eo I 25-16 y 22, y 21, y 20 Gs Eo I 15-8 y 12, y 11, y 10 Gs Eo I 7-0 y 02, y 01, y 00 Gs Eo 26