Lecture 12: Sequential Networks: Timing (contd), Standard Modules CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1
Clock Skew • The clock doesn’t arrive at all registers at the same time • Skew is the difference between two clock edges • Examine the worst case to guarantee that the dynamic discipline is not violated for any register – many registers in a system! 2
Setup time constraint Consider a circuit where the setup constraint is satisfied for R2 when there is no clock skew. 3
Setup time constraint Consider a circuit where the setup constraint is satisfied for R2 when there is no clock skew. Is the setup constraint guaranteed to be satisfied if the rising edge of CLK2 arrives later than that of CLK1, i.e. CLK 2 is delayed (as shown in the figure ? A. Yes B. No 4
Setup Time Constraint with Clock Skew • In the worst case, the CLK2 is earlier than CLK1 CLK1 CLK2 T c ≥ t pcq + t pd + t setup + t skew Q1 D2 C L t pd ≤ T c – ( t pcq + t setup + t skew ) R1 R2 T c CLK1 CLK2 Q1 D2 t pcq t pd t setup t skew 5
Timing Analysis with clock skew Timing Characteristics CLK CLK A t ccq = 30 ps t pcq = 50 ps B t setup = 60 ps X' X C t hold = 70 ps Y' Y D t pd = 3 x 35 ps = 105 ps t pd = 35 ps t cd = 25 ps t cd = 25 ps Setup time constraint: t skew = 50 ps What is the minimum allowable clock period given that the clocks are skewed by 50ps? A. 215ps B. 265 ps C. None of the above 6
Timing Analysis with clock skew Timing Characteristics CLK CLK A t ccq = 30 ps t pcq = 50 ps B t setup = 60 ps X' X C t hold = 70 ps Y' Y D t pd = 3 x 35 ps = 105 ps t pd = 35 ps t cd = 25 ps t cd = 25 ps Setup time constraint: t skew = 50 ps T c ≥ 265 ps f c = 1/ T c =3.77 GHz Without skew we got f c =4.65 GHz 7
Hold Time Constraint with Clock Skew • In the worst case, CLK2 is later than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 t ccq + t cd > t hold + t skew CLK1 t cd > t hold + t skew – t ccq CLK2 Q1 D2 t ccq t cd t skew t hold 8
Hold Time Violation Timing Characteristics Add buffers to the shortest paths: t ccq = 30 ps CLK CLK A t pcq = 50 ps B t setup = 60 ps X' X t hold = 70 ps C Y' Y D t pd = 35 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps t cd = 2 x 25 ps = 50 ps t skew = 50 ps Hold time constraint: t ccq + t cd > t hold + t skew ? (30 + 50) ps > (70 ps +50) ps ? 9
STANDARD MODULES 10
Interconnect: Decoder, Encoder, Mux, DeMux Registers Arbiter Data 1 Memory Bank Mux P1 Address 1 Data P2 Demux n-m Address 2 Mux Address m n 2 m Address k Decoder Data k Pk Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed 11 by the control signals
Part III. Standard Modules Interconnect Modules: 1. Decoder, 2. Encoder 3. Multiplexer, 4. Demultiplexer 12
Decoder Definition: A digital module that converts a binary address to the assertion of the addressed device E (enable) n to 2 n decoder function: y 0 0 I 0 0 y 1 1 . y i = 1 if E= 1 & (I 2, I 1, I 0 ) = i 2 1 I 1 3 . 4 y i = 0 otherwise 5 I 2 2 6 y 7 7 2 n outputs n inputs 2 3 = 8 n= 3 13
1. Decoder: Definition • N inputs, 2 N outputs • One-hot outputs: only one output HIGH at any point in time 2:4 Decoder 11 Y 3 A 1 10 Y 2 A 0 01 Y 1 00 Y 0 A 1 A 0 Y 3 Y 2 Y 1 Y 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 14
Decoder: Logic Diagram (Inside a decoder) y i = m i En En y 0 = 1 if (A 1, A 0 ) = (0,0) & En = 1 A 0 ’ A 1 ’ y 0 2:4 Decoder 11 Y 3 A 1 10 Y 2 y 1 A 0 01 Y 1 00 Y 0 A 1 A 0 Y 3 Y 2 Y 1 Y 0 . 0 0 0 0 0 1 . 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 y 7 = A 1 A 0 En y 3 15
1. Decoder: Definition PI Q: What is the output Y 3:0 of the 2:4 decoder for (A 1 , A 0 ) = (1,0)? 2:4 Decoder 11 Y 3 A. (1, 1, 0, 0 ) A 1 10 Y 2 A 0 01 Y 1 B. (1, 0, 1, 1) 00 Y 0 C. (0, 0, 1, 0) A 1 A 0 Y 3 Y 2 Y 1 Y 0 D. (0, 1, 0, 0) 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 16
Implementing functions using Decoders • OR minterms 2:4 Decoder Minterm 11 AB A 10 AB B 01 AB 00 AB Y = AB + AB = A ⊕ B Y 17
Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 3-input decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) ii) f 2 (a,b,c) = Σ m(2,3), iii) f 3 (a,b,c) = Σ m(0,5,6) 18
Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 2:4 decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) How many 2:4 decoders are required to implement the above function? A. One B. Two C. Three D. Four 19
Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 1:2 decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) How many 1:2 decoders are required to implement the above function? A. Three B. Four C. Six D. Seven 20
Tree of Decoders Implement a 4-2 4 decoder with 3-2 3 decoders. y 0 0 d I 0 y 1 1 2 c I 1 3 4 5 b I 2 6 y 7 7 y 8 0 I 0 y 9 1 2 I 1 3 4 5 I 2 6 y 15 7 a 21
Tree of Decoders Implement a 6-2 6 decoder with 3-2 3 decoders. En En y 0 I 2, I 1, I 0 D 0 y 7 y 8 I 5, I 4, I 3 I 2, I 1, I 0 D 1 y 15 … … y 56 I 2, I 1, I 0 D 7 y 63 22
PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following? A. 1:2 decoders and OR gates B. 2:4 decoders and OR gates C. 3:8 decoders and OR gates D. None of the above E. All of the above 23
Interconnect: Decoder, Encoder, Mux, DeMux Processors Arbiter Data 1 Memory Bank Mux P1 Address 1 Data P2 Demux n-m Address 2 Mux Address m n 2 m Address k Decoder Data k Pk Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed 24 by the control signals
2. Encoder • Definition (What is it?) • Logic Diagram (How is it realized?) 25
2. Encoder: Definition En 8 inputs 3 outputs I 0 0 y 0 0 1 2 y 1 1 3 4 2 y 2 5 6 I 7 7 A At most one I i = 1. (y n-1 ,.., y 0 ) = i if I i = 1 & E n = 1 (y n-1 ,.., y 0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. I i = 1 A = 0 otherwise. 26
Encoder: Logic Diagram En En y 0 y 1 I 2 I 1 I 3 I 3 I 5 I 6 I 7 I 7 En En y 2 I 4 A I 0 I 5 I 1 . I 6 . I 7 I 6 I 7 27
Multiplexer • Definition • Logic Diagram • Application 28
Interconnect: Decoder, Encoder, Mux, DeMux Processors Arbiter Data 1 Memory Bank Mux P1 Address 1 Data P2 Demux n-m Address 2 Mux Address m n 2 m Address k Decoder Data k Pk Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed 29 by the control signals
Multiplexer Definition: Example En 0 D 0 S 1 S 0 y D 1 1 y 2 D 2 D 3 3 S 1 S 0 Selects between one of N inputs to connect to the output. log 2 N -bit select input – control input 30
PI Q: What is the output of the following MUX for the given inputs and En=1, S=1? A. 0 B. 1 En =1 C. Can’t say y 0 1 0 1 S=1 31
Multiplexer (Mux): Example 2:1 Mux S D 0 0 Y D 1 1 S D 1 D 0 Y S Y D 0 0 0 0 0 0 D 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 32
Multiplexer Application • Mux for a Boolean function with truth table as input A B Y 0 0 0 0 1 0 1 0 0 1 1 1 Y = AB A B 00 01 Y 10 11 33
Multiplexer: Application A A Y A B Y 0 0 0 0 0 0 0 1 0 Y Y = AB 1 0 0 1 1 B B 1 1 1 34
Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with an 8-input Mux. Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 35
Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with an 8-input Mux. En Id a b c f 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 2 2 0 1 0 - 0 3 y 3 0 1 1 0 0 4 0 5 4 1 0 0 0 6 0 5 1 0 1 0 7 1 6 1 1 0 0 S 2 S 1 S 0 7 1 1 1 1 a b c 36
Example 2: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 4-input Muxes. Id a b c f En 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 0 3 0 1 1 0 1 4 1 0 0 0 y 5 1 0 1 0 2 6 1 1 0 0 7 1 1 1 1 3 S 1 S 0 D (c) a b D 0 (c) =1 D 1 (c) =0 D 2 (c) =0 D 3 (c) =c 37
Example 2: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 4-input Muxes. En D (c) a b c = 0 c = 1 1 0 D 0 (c) =1 0 0 1 1 0 1 0 1 - 0 D 1 (c) =0 y 1 0 0 0 D 2 (c) =0 0 2 1 1 0 1 D 3 (c) =c c 3 S 1 S 0 a b 38
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