Lecture 15: Sequential Networks – Finite State Machines Moore and Mealy (contd) CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1
QUIZ – NO TALKING – NO NOTES Q1: True or False: Can the operation of a NAND gate be implemented using ONLY the following function? Assume you can modify the function by fixing one or more inputs as (1 or 0). f(a,b,c)= ab+a’b’ +c A. True B. No
QUIZ – NO TALKING – NO NOTES Q2: Which of the following functionalities is achieved by the given circuit for the input combination S’R’=(1,0)? A. Memory: Outputs (Q, Q’) remain unchanged B. Set to zero: (Q, Q’)= (0,1) C. Set to one: (Q, Q’)= (1,0) D. None of the above
QUIZ – NO TALKING – NO NOTES Q3: The following timing diagram corresponds to which of the following latch or flip-flops? (Assume the output is initially 1) CLK Input Output A. D-latch B. D-flip flop C. T- flip flop D. JK- flip flop
QUIZ – NO TALKING – NO NOTES Q4: Which of the following is true about the given FSM? A. It is a Moore machine B. It is a Mealy machine with two outputs C. It is a Mealy machine that detects the input pattern 0001 in the input sequence by setting the output to 1 D. It is a Mealy machine that detects the input pattern 1101 in the input sequence by setting the output to 1 E. None of the above
QUIZ – NO TALKING – NO NOTES Q5: For the given Mealy circuit, which of the following is true if x(t) transitions from 1 to 0 at t 1 as shown in the following timing diagram ? x(t) y(t) C1 C2 x(t) t 1 CLK S(t) Mealy Machine A. Only the state: S(t) can change at t 1 B. Only the output: y(t) can change at t 1 C. y(t) will change at t 1 only if S(t) also changes at t 1 D. S(t) and y(t) can only change at the next rising edge of the clock after t 1
Mealy implementation of Pattern Recognizer ‘001’ 1/1 1/0 0/0 0/0 S0 S1 S2 0/0 1/0 x(t) Q: What information do we need to design C1? y(t) A. State table showing (current input x(t), C1 C2 current state S(t) vs. next state, S(t+1)) B. State table showing (current input, current state vs. current output y(t)) CLK S(t) C. State table showing (current input, current state vs. current output y(t) and next state) Mealy Machine D. None of the above 7
State Diagram => State Table with State Assignment 1/1 1/0 0/0 0/0 S0 S1 S2 0/0 1/0 x(t) y(t) C1 C2 CLK S(t) Q 1 (t+1)Q 0 (t+1), y Mealy Machine State Assignment S(t)\x 0 1 S(t)\x 0 1 00 01,0 00,0 S0 S1,0 S0,0 S0: 00 S1: 01 01 10,0 00,0 S1 S2,0 S0,0 S2: 10 10 10,0 00,1 8 S2 S2,0 S0,1
State Diagram => State Table => Excitation Table => Circuit id Q 1 Q 0 x D 1 D 0 y Q 1 (t) Q 0 (t)\x 0 1 00 01,0 00,0 000 0 0 1 0 01 10,0 00,0 001 1 0 0 0 10 10,0 00,1 010 2 1 0 0 011 x(t) 3 0 0 0 100 4 1 0 0 y(t) C1 C2 101 5 0 0 1 CLK 110 6 X X X S(t) Mealy Machine 111 7 X X X 9
State Diagram => State Table => Excitation Table => Circuit Q 0 id Q 1 Q 0 x D 1 D 0 y D 1 (t): 0 2 6 4 000 0 0 1 0 0 1 X 1 001 1 3 7 5 1 0 0 0 0 0 X 0 x(t) 010 2 1 0 0 Q 1 011 3 0 0 0 D 1 (t) = x’Q 0 + x’Q 1 100 4 1 0 0 D 0 (t)= Q’ 1 Q’ 0 x’ 101 5 0 0 1 y= Q 1 x 110 6 X X X 111 7 X X X 10
State Diagram => State Table => Excitation Table => Circuit Q’ 1 Q 0 D 0 Q Q’ 0 D x’ Q’ Q 1 y x’ D 1 Q D Q 0 Q’ Q 1 x x(t) D 1 (t) = x’Q 0 + x’Q 1 y(t) C1 C2 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x CLK S(t) Mealy Machine 11
State Diagram => State Table => Excitation Table => Netlist 1/1 1/0 0/0 0/0 S0 S1 S2 0/0 1/0 Q’ 1 Q 0 D 0 Q Q’ 0 D x’ Q’ Q 1 y x’ D 1 Q D Q 0 Q’ Q 1 x iClicker: The relation between the above state diagram and sequential circuit. A. One to one. B. One to many C. None of the above 12
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