Lecture 13: Standard Modules CSE 140: Components and Design - PowerPoint PPT Presentation

Lecture 13: Standard Modules CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 3-input decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) ii) f 2 (a,b,c) = Σ m(2,3), iii) f 3 (a,b,c) = Σ m(0,5,6) 2

Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 2:4 decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) How many 2:4 decoders are required to implement the above function? A. One B. Two C. Three D. Four 3

Decoder Application: universal set {Decoder, OR} Example: Implement the following functions with a 1:2 decoder and OR gates. i) f 1 (a,b,c) = Σ m(1,2,4) How many 1:2 decoders are required to implement the above function? A. Three B. Four C. Six D. Seven 4

Tree of Decoders Implement a 4-2 4 decoder with 3-2 3 decoders. y 0 0 d I 0 y 1 1 2 c I 1 3 4 5 b I 2 6 y 7 7 y 8 0 I 0 y 9 1 2 I 1 3 4 5 I 2 6 y 15 7 a 5

Tree of Decoders Implement a 6-2 6 decoder with 3-2 3 decoders. En En y 0 I 2, I 1, I 0 D 0 y 7 y 8 I 5, I 4, I 3 I 2, I 1, I 0 D 1 y 15 … … y 56 I 2, I 1, I 0 D 7 y 63 6

PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following? A. 1:2 decoders and OR gates B. 2:4 decoders and OR gates C. 3:8 decoders and OR gates D. None of the above E. All of the above 7

Interconnect: Decoder, Encoder, Mux, DeMux Processors Arbiter Data 1 Memory Bank Mux P1 Address 1 Data P2 Demux n-m Address 2 Mux Address m n 2 m Address k Decoder Data k Pk Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed 8 by the control signals

2. Encoder • Definition (What is it?) • Logic Diagram (How is it realized?) 9

2. Encoder: Definition En 8 inputs 3 outputs I 0 0 y 0 0 1 2 y 1 1 3 4 2 y 2 5 6 I 7 7 A At most one I i = 1. (y n-1 ,.., y 0 ) = i if I i = 1 & E n = 1 (y n-1 ,.., y 0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. I i = 1 A = 0 otherwise. 10

Encoder: Logic Diagram En En y 0 y 1 I 2 I 1 I 3 I 3 I 5 I 6 I 7 I 7 En En y 2 I 4 A I 0 I 5 I 1 . I 6 . I 7 I 6 I 7 11

Multiplexer • Definition • Logic Diagram • Application 12

Interconnect: Decoder, Encoder, Mux, DeMux Processors Arbiter Data 1 Memory Bank Mux P1 Address 1 Data P2 Demux n-m Address 2 Mux Address m n 2 m Address k Decoder Data k Pk Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed 13 by the control signals

Multiplexer Definition: Example En 0 D 0 S 1 S 0 y D 1 1 y 2 D 2 D 3 3 S 1 S 0 Selects between one of N inputs to connect to the output. log 2 N -bit select input – control input 14

PI Q: What is the output of the following MUX for the given inputs and En=1, S=1? A. 0 B. 1 En =1 C. Can’t say y 0 1 0 1 S=1 15

Multiplexer (Mux): Example 2:1 Mux S D 0 0 Y D 1 1 S D 1 D 0 Y S Y D 0 0 0 0 0 0 D 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 16

Multiplexer Application • Mux for a Boolean function with truth table as input A B Y 0 0 0 0 1 0 1 0 0 1 1 1 Y = AB A B 00 01 Y 10 11 17

Multiplexer: Application A A Y A B Y 0 0 0 0 0 0 0 1 0 Y Y = AB 1 0 0 1 1 B B 1 1 1 18

Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with an 8-input Mux. Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 19

Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with an 8-input Mux. En Id a b c f 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 2 2 0 1 0 - 0 3 y 3 0 1 1 0 0 4 0 5 4 1 0 0 0 6 0 5 1 0 1 0 7 1 6 1 1 0 0 S 2 S 1 S 0 7 1 1 1 1 a b c 20

Example 2: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 4-input Muxes. Id a b c f En 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 0 3 0 1 1 0 1 4 1 0 0 0 y 5 1 0 1 0 2 6 1 1 0 0 7 1 1 1 1 3 S 1 S 0 D 0 (c) =1 a b D 1 (c) =0 D 2 (c) =0 D 3 (c) =c 21

Example 2: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 4-input Muxes. En D (c) a b c = 0 c = 1 1 0 D 0 (c) =1 0 0 1 1 0 1 0 1 - 0 D 1 (c) =0 y 1 0 0 0 D 2 (c) =0 0 2 1 1 0 1 D 3 (c) =c c 3 S 1 S 0 a b 22

Example 3: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 2- input Muxes. Id a b c f En 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 0 y 3 0 1 1 0 4 1 0 0 0 1 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 a 23

Example 3: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 2- input Muxes. D 1 (b,c) b c = 0 c = 1 En 0 0 0 l 1 (0) = 0 1 0 1 l 1 (c) = c b ’ 0 y D 0 (b,c) = b ’ D 1 (b,c) = bc 1 1 - 0 0 c c 1 0 0 1 a b b 24

Example 3: Given f (a,b,c) = Σ m (0,1,7) + Σ d(2), implement with 2- input Muxes. D 1 (b,c) En b c = 0 c = 1 En b ’ 0 0 0 l 1 (0) = 0 0 1 y 0 1 l 1 (c) = c 0 1 0 c 1 a b 25

4. Demultiplexers En x Control Input 26

4. Demultiplexers En y i = x if i = (S n-1 , .. , S 0 ) & En = 1 y i = 0 otherwise y 2n-1 -y 0 x S(n-1,0) Control Input 27