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Adders Lecture 12 CS301 Administrative Read Appendix C.5, C.7-C.10 Program #1 due 10/24 FP Bias Infinity is represented as w exponent is all 1s w significand is all 0s Review MUX DeMux Decoder Encoder

  1. Adders Lecture 12 CS301

  2. Administrative • Read Appendix C.5, C.7-C.10 • Program #1 due 10/24

  3. FP Bias • Infinity is represented as w exponent is all 1s w significand is all 0s

  4. Review • MUX • DeMux • Decoder • Encoder

  5. Combinational Logic • Half-Adder w No carry in Carry A B Sum Out 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 A ⊕ B AB

  6. 1-bit Full Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in

  7. Combinational Logic • Full Adder Note: C out = (b C in ) + (a C in ) + (a b) + (a b C in ) = (b C in ) + (a C in ) + (a b) = (a b) + (a + b) C in

  8. Ripple Carry Adder • Construct n-bit adder with n 1-bit adders • Delay is problem • Faster alternative: w Carry-lookahead adder

  9. Designing connections • Problem: Ripple-carry adder is too slow w Each carry must wait for all previous units to complete execution • Solution:

  10. Designing connections • Problem: Ripple-carry adder is too slow w Each carry must wait for all previous units to complete execution • Solution: w Quickly get information for carries w Compute carries in parallel

  11. 1b Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in w C out = AB + AC in + BC in

  12. Carry Look-ahead We already know: c i+1 = (b i Ÿ c i ) + (a i Ÿ c i ) + (a i Ÿ b i ) = (a i Ÿ b i ) + c i Ÿ (a i + b i )

  13. Carry Look-ahead We already know: c i+1 = (b i Ÿ c i ) + (a i Ÿ c i ) + (a i Ÿ b i ) = (a i Ÿ b i ) + c i Ÿ (a i + b i ) Generate Propagate = Gi + Ci Ÿ Pi Let’s calculate c i+1 without waiting for c i

  14. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0

  15. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0

  16. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0

  17. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1

  18. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

  19. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

  20. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

  21. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 P0 G0 C1 P3 G3 P2 G2 P1 G1 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

  22. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2

  23. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2

  24. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

  25. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

  26. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

  27. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

  28. Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

  29. Why is it Faster?

  31. Why is it Faster? 4 th bit waits only for p&g to be calculated, not all of the • computations from bits 0-2 Only three levels of computation • C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2 w Gi and Pi w AND w OR

  32. The Next Step A[12-15] A[8-11] A[4-7] A[0-3] B[0-3] B[12-15] B[8-11] B[4-7] 4-bit ALU 4-bit ALU 4-bit ALU 4-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic Now what is the equation for Pi & Gi? They are for the 4-bit ALU, not just one bit!

  33. Basic Memory Cells and Sequential Logic

  34. Sequential Logic and Clocks • Sequential logic retains state • Clocks specify when that state should be updated • System using clocks called synchronous

  35. Clock Falling • Signal with fixed edge cycle time ( T cycle) Rising edge • Frequency: 1/ T cycle • T cycle has two parts delineated by two edges T cycle w Clock high w Clock low

  36. Clocks (cont.)

  37. Memory Elements • All memory elements store state w Output depends both on inputs and the value stored inside the memory element • Thus: All logic blocks containing memory elements contain state and are sequential!

  38. Unclocked Latch

  39. Clocked Latch

  40. D Flip-Flop • D flip flop stores 1 bit of data • Created from 2 edge triggered D latches • Only takes in new inputs when clock is high

  41. Register D flip-flop allows us to store 1 bit • Programmers don’t programming in bits, but • w char = 8 b w integer = 32 b w ... String n D flip-flops together to store n bits • b3 b2 b1 b0 4b register implement with D flip-flops

  42. Register Files • Contains set of registers accessed by register num w Input: register number w Output: data in register n entry register file

  43. Register Files • Components w Array of registers built from flip-flops • Port w Access point w Read port § register num w Write port § register num, clock, data 2 read ports / 1 write port

  44. Register File: 
 Read Ports

  45. Register File: 
 Write Port

  46. Comparator • Comparator has three output lines w A<B w A=B w A>B

  47. Comparator

  48. Comparator

  49. Comparator

  50. We Almost Have All the Pieces • Inverter, AND, OR • Multiplexor and demultiplexor • Decode and encoder • Comparator • Ripple carry adder and carry lookahead adder w Half and full adder • Register file w Registers w D flip flop

  51. Arithmetic Logic Unit • Circuitry that does arithmetic (+/-) and logical operations (AND/OR) • MIPS has 32b quantities so ALU needs to handle 32b numbers • Combine 32 1-b ALUs to create 32b ALU

  52. AND/OR

  53. 1b Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in

  54. 1b ALU

  55. 32b ALU

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