EITF35: Introduction to Structured VLSI Design Part 3.1.2: VHDL-4 Liang Liu liang.liu@eit.lth.se 1 Lund University / EITF35/ Liang Liu
Outline Handling Large Designs: Hierarchical Component Generics Configurations Library and Package 2 Lund University / EITF35/ Liang Liu
Hierarchical Design Hierarchical design • Divided-and-conquer strategy • Divide a system into smaller parts • Constructs each module independently • Recursively: division process can be applied repeatedly and the modules can be further decomposed • Connect each part structrually Conquer one problem each time 3 Lund University / EITF35/ Liang Liu
Hierarchical Design Example: repetitive-addition multiplier 4 Lund University / EITF35/ Liang Liu
Hierarchical Design: Advantage Complexity management • Focus on a manageable portion of the system, and analyze, design and verify each module in isolation • Construct the system concurrently by a team of designers Design reuse • Use predesigned modules or third-party cores (e.g., IP cores) • Use the same module in different design or your future design 5 Lund University / EITF35/ Liang Liu
VHDL Supporting Hierarchical Design Relevant VHDL constructs • Component • Generic • Configuration • Library • Package • Subprogram • The component , generic and configuration constructs help to describe a hierarchical design. • The library , package , and subprogram help the management of complicated code 6 Lund University / EITF35/ Liang Liu
Outline Handling Large Designs: Hierarchical Component Generics Configurations Library and Package 7 Lund University / EITF35/ Liang Liu
Component Hierarchical design usually shown as a block diagram • Specify the module used • The interconnections among these parts VHDL component describes structural description in text How to use a component? • Component declaration • Component instantiation 8 Lund University / EITF35/ Liang Liu
Component Declaration Component declaration provides information about the external interface of a component • The input and output ports • Relevant parameters The information is similar to that provided in an entity declaration component component_name is generic( generic_declaration; generic_declaration; … ); port ( port_declaration; port_declaration; … ); end component 9 Lund University / EITF35/ Liang Liu
Component instantiation Instantiate an instance of a component • Provide a generic value • Map formal signals to actual signals Syntax instance_label: component_name generic map( generic_association; generic_association; o_q i_en ) port map( o_pulse port_association; i_clk port_association; ); Port Map rst port_name => signal_name 10 Lund University / EITF35/ Liang Liu
Component: Design Example Mod- 100 counter: 0,1,2, … 98,99,0,1,2, … 98,99,0 Step1: block diagram design • Design two mod-10 counter • One for one-digit, one for ten-digit 11 Lund University / EITF35/ Liang Liu
Component: Design Example Step2: component design ... 0 1 2 9 0 r_reg en pulse T 12 Lund University / EITF35/ Liang Liu
Component: Design Example Step3: component declaration 13 Lund University / EITF35/ Liang Liu
Component: Design Example Step4: Instantiate and connect Suggestion: 1. Use name association (one-to-one mapping) 2. Draw block diagram or make connection table! 14 Lund University / EITF35/ Liang Liu
Massive MIMO 15 Lund University / EITF35/ Liang Liu
Outline Handling Large Designs: Hierarchical Component Generics Configurations Library and Package 16 Lund University / EITF35/ Liang Liu
Generic Mechanism to pass info into an entity/component Declared in entity declaration and then can be used as a constant in port declaration and architecture body Assigned a value when the component is instantiated Like a parameter, but HAS TO BE a CONSTANT Example: step1 declaration 17 Lund University / EITF35/ Liang Liu
Generic Mechanism to pass info into an entity/component Declared in entity declaration and then can be used as a constant in port declaration and architecture body Assigned a value when the component is instantiated Like a parameter, but HAS TO BE a CONSTANT Example: step1 declaration Declare before port Can be used in port declaration 18 Lund University / EITF35/ Liang Liu
Generic Mechanism to pass info into an entity/component Declared in entity declaration and then can be used as a constant in port declaration and architecture body Assigned a value when the component is instantiated Like a parameter, but HAS TO BE a CONSTANT Example: step1 declaration Limit the number of generics in each entity Do NOT use generic for connecting signals 19 Lund University / EITF35/ Liang Liu
Generic Example: step 2 utilization Can also be used to parameterize signals within an architecture 20 Lund University / EITF35/ Liang Liu
Generic Example: step3 instantiation Note the semicolon “;” 21 Lund University / EITF35/ Liang Liu
Outline Handling Large Designs: Hierarchical Component Generics Configurations Library and Package 22 Lund University / EITF35/ Liang Liu
Configuration Bind a component with an entity and an architecture • Bind a component with a design entity • Bind the design entity with a body architecture • Default binding: use same name Not supported by all synthesis software Suggestion: Use only in testbench • Testbench is reused by declaring a different configuration • Examples: Behavorial model Gate-level model 23 Lund University / EITF35/ Liang Liu
Configuration Daclaration 24 Lund University / EITF35/ Liang Liu
Configuration-Example entity name and component name differs configuration THREE of FULLADDER is for STRUCTURAL for INST_HA1 , INST_HA2 : HA use entity WORK. HALFADDER (CONCURRENT); end for; for INST_XOR : XOR use entity WORK. XOR2D1 (CONCURRENT); end for; end for; end THREE; 25 Lund University / EITF35/ Liang Liu
Suggestion: One entity per file, file name the same with entity name Top-level file as a simple integration of smaller building blocks Do NOT put critical path between component 26 Lund University / EITF35/ Liang Liu
Outline Handling Large Designs: Hierarchical Component Generics Configurations Library and Package 27 Lund University / EITF35/ Liang Liu
Libraries and Packages Used to declare and store: • Components • Type declarations • Functions • Procedures Packages and libraries provide the ability to reuse constructs in multiple entities and architectures 28 Lund University / EITF35/ Liang Liu
Libraries Two predefined libraries are the IEEE and WORK libraries WORK is the default library IEEE standard library contains the IEEE standard design units. • std_logic_1164 • numeric_std IEEE is non-default library, must be declared: library ieee ; Design units within the library must also be made visible via the use clause. use ieee.std_logic_1164.all; use ieee.numeric_std.all; 29 Lund University / EITF35/ Liang Liu
Packages Declarations in an architecture • Consist of the declarations of constants, data types, components, functions and so on • Must be duplicated in many different design units, for hierarchical design Packages • Organize and store declaration information Data type Function constant 30 Lund University / EITF35/ Liang Liu
Packages Declaration: Example library ieee; use ieee.std_logic_1164.all; package my_package is type binary is (on, off); constant C_ROUTING_ID_BITS: integer := 3; component counter_dec is generic (constant WIDTH: integer); port ( clk_in, rst_n: in std_logic; en: in std_logic; q: out std_logic_vector (WIDTH-1 downto 0); puls: out std_logic ); end component; end my_package; 31 Lund University / EITF35/ Liang Liu
Package: How to use? A package is made visible using the use clause use library_name.package_name.item use work.my_package.binary; use work.my_package.counter_dec; ... entity declaration ... ... architecture declaration ... use the binary and counter_dec declarations use work.my_package.all; ... entity declaration ... ... architecture declaration ... use all of the declarations in package my_package 32 Lund University / EITF35/ Liang Liu
Reading Advice FSMD: RTL Hardware Design Using VHDL , Chapter 11, P373-P420 Hierarchical VHDL: RTL Hardware Design Using VHDL, Chapter 13, P473-P498 33 Lund University / EITF35/ Liang Liu
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