PID meeting Electronics Integration Christophe Beigbeder PID - PowerPoint PPT Presentation

PID meeting Electronics Integration Christophe Beigbeder PID meeting 1 Juin 1st 2010

Electronics is split in two parts : - one directly mounted on the PM base receiving the PM signal and processing it with TDC/ADC - the other one concentrates and pack all the channels to send data to the DAQ Electronics on the detector  Mechanical constraints: Fixing the module on the PM base. Dismounting issues.  Thermal constraints : Door closed gives problems of cooling.  Fans on the module as G Varner’s ?  Global heat extraction…. Christophe Beigbeder PID meeting 2 Juin 1st 2010

Detector : 12 sectors -> ~ 36 k channels 1 MAPMT footprint = > 64 channels 5cm 1 Sector -> 48 * 64 = 3072 Channels. 1 to 12 sectors per crate Concentrator Crate FE PGA ASIC TDC ADC 16 to 128-channel per board -> 20 to 160 boards per sector. Cat5 cable From TTC optical Power Supply To DAQ optical ECS electrical Christophe Beigbeder PID meeting 3 Juin 1st 2010

Other possible solutions … Long boards : 80 channels . Mechanical issues for a precise adjustment base to base. This granularity has a impact in case of failure. No long a Pm considered as a cell element but a row of 5 pms. Christophe Beigbeder PID meeting 4 Juin 1st 2010

Cooling issue  A rough estimation gives :  Fe : 500 mW / 16 channels  Pga : 1 W / 16 channels  TDC : 500 mW /16 channels  ` + glue = > Total 3 W / 16 channels  = > Sector ( ~ 3Kchannels ) = ~ 600 W  = > 7 KW in total Christophe Beigbeder PID meeting 5 Juin 1st 2010

Cooling issue  From documentation  Q = ( 3.1 P) / T  Q= airflow in m3 / h  P = Dissipated power ( W)  T = Temperature change at given air flow  -> 600 W power , a specified difference T = 10 degre requires a airflow of 190 m3 /h Christophe Beigbeder PID meeting 6 Juin 1st 2010

Mechanical issues  Boards/ Module insertion/desinsertion issues Christophe Beigbeder PID meeting 7 Juin 1st 2010

Mechanical constraints  Pins issue : Male -> Female on the “backplane “ Christophe Beigbeder PID meeting 8 Juin 1st 2010

FE board synopsis 16 Channels Jtag from MaPmt * 16 (?) A c t e l P G A 1 Raw ADC Fe Asic 16 Channels ADC 12 bits/ Fast Charge Sample and 56 Mhz Shaper 12 bits/ Amp Amp Hold Event Event Packing Formater TDC Law Walk Discriminator 16 Chs 100 ps PM output FE_Pga connectors I2C I2C I2C Probe Output MUX ECS Specs I2C Power Regulators/ Supplies Clock distibution Delatcher elements Version 1/03/2010 Christophe Beigbeder PID meeting 9 Juin 1st 2010

SNATS : new design Gray counter SNATS2 Clk@160Mhz 48 bits 48 *16 48 Reg Clear 7-16 Derandomizer Synchro 16 16 Fifo Data[15:0]@80Mhz Clear Packing [1-4 words] *16 Hit 5 FE 5 DLL Reg DLL @160Mhz Clear Per channel Readout dead time State Machine Max speed 1Mhz Instantaneous Global State machine Sync Dead time Clk@80Mhz Push the data Christophe Beigbeder PID meeting 10 Juin 1st 2010

Summary of the SNATS evolution : • Redesign of the readout and a few improvements on the Front end part • Programmable number of bits for the time counter. • New derandomizing FIFOs : depth of 16/32 events ( each of 4 * 16-bit data word) • Data push at the output Run end 2010 . AMS .35 um technology. Chip delivered first quarter of 2011 We have to think of the way to run the chip together with the FE ASIC and to match the analog pulse converted by the ADC with the hit time -> Design and simulation in the FPGA Also have to interface the FPGA with the Proposa sal for t he e Elec ect ronics s Trigger er and DAQ archit ect ure to get inside the front end buffer. The data are output with a latency depending on the rate per channel and the occupancy of the chip. 2 Clk cycles to output the data ( Derandomizer FIFO to PGA @ 84 MHz (56* 1.5) ) followed by 2 Clk cycles for each other fired Channel. Latency from 2 Clk cycles to 32 Clk cycles ( 2.5 MHz per channel ) Christophe Beigbeder PID meeting 11 Juin 1st 2010