Paper presentation Ultra-Portable Devices Paper: Shanti Pavan, - PowerPoint PPT Presentation

Paper presentation – Ultra-Portable Devices Paper: Shanti Pavan, Nagendra Krishnapura, et al. A Power Optimized Continuous- Time Δ∑ ADC for Audio Applications, Journal of Solid State Circuits, Vol. 43, No. 2, pp 351-360, Feb 2008. Presented by: Dejan Radjen 2010-03-23 Paper Presentation - Ultra Portable Devices 1

Outline • Introduction • Choice of Architecture • Circuit Design • Measurement Results • Summary and Conclusions 2010-03-23 Paper Presentation - Ultra Portable Devices 2

Introduction • Traditional Δ∑ -modulators were discrete time designs • Continuous time Δ∑ -modulators offer following advantages – Implicit anti alias filtering – More relaxed amplifier GBW-requirements • Several strategies employed to reduce power consumption – Large input signal (3 V p-p differential) – Chosen NTF results in performance tolerant against comparator offsets – Excess delay compensation 2010-03-23 Paper Presentation - Ultra Portable Devices 3

Choice of Architecture • A single loop topology is chosen • The 3:rd order NTF chosen ensures an SQNR well above 92 dB (in a 24 kHz bandwidth) • Resulting SQNR ensures that the design is limited by thermal noise 2010-03-23 Paper Presentation - Ultra Portable Devices 4

Choice of Architecture Multi bit vs. single bit quantizer • Lower in-band quantization noise • Lower noise due to clock jitter • Lower slew rate requirements in the loop filter 2010-03-23 Paper Presentation - Ultra Portable Devices 5

Choice of Architecture Choosing the Noise Transfer Function 2010-03-23 Paper Presentation - Ultra Portable Devices 6

Choice of Architecture Choosing the Noise Transfer Function 2010-03-23 Paper Presentation - Ultra Portable Devices 7

Choice of Architecture Effect of systematic RC time-constant deviation 2010-03-23 Paper Presentation - Ultra Portable Devices 8

Choice of Architecture Modulator architectures Feed forward Distributed feedback 2010-03-23 Paper Presentation - Ultra Portable Devices 9

Circuit Design Loop Filter Summing Amplifier 2010-03-23 Paper Presentation - Ultra Portable Devices 10

Circuit Design Excess loop delay • Poles in the opamps introduce excess delay in the loop filter • If the feedback pulse ends outside the clock cycle, the order of the system is increased 2010-03-23 Paper Presentation - Ultra Portable Devices 11

Circuit Design Conventional excess delay compensation 2010-03-23 Paper Presentation - Ultra Portable Devices 12

Circuit Design Proposed excess delay compensation 2010-03-23 Paper Presentation - Ultra Portable Devices 13

Circuit Design Opamp for the first integrator 2010-03-23 Paper Presentation - Ultra Portable Devices 14

Circuit Design Opamp for the rest of the integrators 2010-03-23 Paper Presentation - Ultra Portable Devices 15

Circuit Design Block diagram of the quantizer 2010-03-23 Paper Presentation - Ultra Portable Devices 16

Circuit Design Comparator schematic and timing 2010-03-23 Paper Presentation - Ultra Portable Devices 17

Circuit Design Effect of comparator random offset on SNDR 2010-03-23 Paper Presentation - Ultra Portable Devices 18

Circuit Design Digital back-end and DEM logic 2010-03-23 Paper Presentation - Ultra Portable Devices 19

Circuit Design Implementation of the DAC-cell 2010-03-23 Paper Presentation - Ultra Portable Devices 20

Measurement Results SNR, SNDR and dynamic range 2010-03-23 Paper Presentation - Ultra Portable Devices 21

Measurement Results Output spectrum 2010-03-23 Paper Presentation - Ultra Portable Devices 22

Measurement Results Figure of merit 2010-03-23 Paper Presentation - Ultra Portable Devices 23

Measurement Results 2010-03-23 Paper Presentation - Ultra Portable Devices 24

Measurement Results 2010-03-23 Paper Presentation - Ultra Portable Devices 25

Summary and Conclusions • A CT Δ∑ - modulator with a multi bit quantizer was designed to improve on the single bit modulators • NTF was chosen to achieve a design immune to RC – time constant variation, jitter and comparator offsets • Several measures were taken to reduce power consumption • A new compensation technique was used to compensate for excess loop delay 2010-03-23 Paper Presentation - Ultra Portable Devices 26