�������������������������������� Noise in Switched�Capacitor Circuits 17 March 2014 Trevor Caldwell trevor.caldwell@analog.com What you will learn# � How to analyze noise in switched�capacitor circuits � Significance of switch noise vs. OTA noise Power efficient solution Impact of OTA architecture � Design example for �Σ �Σ �Σ �Σ modulator 2
Review � Previous analysis of kT/C noise (ignoring OTA/opamp noise) Phase 1: kT/C 1 noise (on each side) Phase 2: kT/C 1 added to previous noise (on each side) Total Noise (input referred): 2kT/C 1 Differentially: 4kT/C 1 3 Review � SNR (differential) Total noise power: 4kT/C 1 Signal power: (2V) 2 /2 SNR: V 2 C 1 /2kT � SNR (single�ended) Total noise power: 2kT/C 1 (sampling capacitor C 1 ) Signal power: V 2 /2 (signal from �V to V) SNR: V 2 C 1 /4kT 4
Noise in an Integrator � Two noise sources V C1 and V OUT V C1 : Represents input�referred sampled noise on input switching transistors + OTA V OUT : Represents output�referred (non�sampled) noise from OTA 5 Thermal Noise in OTAs � Single�Ended Example 2 = = = = γ γ γ γ � 4 �� � Noise current from each transistor is � � γ = γ γ γ = = = 2 / 3 Assume I n3 I n4 M 3 M 4 V OUT V IN + I n1 I n2 V IN � M 1 M 2 I n5 M 5 V B1 6
Thermal Noise in OTAs � Single�Ended Example Thermal noise in single�ended OTA Assuming paths match, tail current source M 5 does not contribute noise to output 8 �� PSD of noise voltage in M 1 (and M 2 ): 3 � � 1 8 ��� PSD of noise voltage in M 3 (and M 4 ): � 3 2 3 � � 1 Total input referred noise from M 1 � M 4 � 16 �� 16 �� = = = = + + + + = = = = � 1 � 3 � � �� , � 3 � � 3 � � 1 � 1 � 1 Noise factor n f depends on architecture 7 OTA with capacitive feedback � Analyze output noise in single�stage OTA Use capacitive feedback in the amplification / integration phase of a switched�capacitor circuit 8
OTA with capacitive feedback � Transfer function of closed loop OTA � � = = = = = = = = � � ( ) ��� + + + + � ω ω ω ω � 1 / � �� , � where the DC Gain and 1st�pole frequency are β β β β � 1 ω ω = ω ω = = = ≈ ≈ ≈ ≈ = = = = + + + + � 1 � 1 � / � � β β β β 1 2 � � Load capacitance C O depends on the type of OTA – for a single�stage, it is C L +C 1 C 2 /(C 1 +C 2 ), while for a two� stage, it is the compensation capacitor C C 9 OTA with capacitive feedback � Integrate total noise at output ∞ ∞ ∞ ∞ ∫ ∫ ∫ ∫ 2 = = π π 2 = = π π � � ( ) � � � ( 2 � ) �� ��� � �� , 0 ω ω ω ω 16 �� � = = = = � � 2 � 3 � 4 � 1 4 �� � = = = = β β � β β 3 � � 4 �� � Minimum output noise for β β =1 is β β � 3 � � Not a function of g m1 since bandwidth is proportional to g m1 while PSD is inversely proportional to g m1 10
OTA with capacitive feedback � Graphically# Noise is effectively filtered by equivalent brick wall response with cut�off frequency π π π π f o /2 (or ω ω o /4 or 1/4 τ ω ω τ ) τ τ Total noise at V OUT is the integral of the noise within the brick wall filter (area is simply π π π π f o /2 x 1/ β β 2 ) β β 11 Sampled Thermal Noise � What happens to noise once it gets sampled? Total noise power is the same Noise is aliased – folded back from higher frequencies to lower frequencies PSD of the noise increases significantly 12
Sampled Thermal Noise � Same total area, but PSD is larger from 0 to f S /2 2 � � � 2 4 �� 1 = = = = � �� , = = = = = = = = � ( ) � ��� � ���� τ τ β β � τ τ β β 4 � / 2 � / 2 3 � � / 2 � � � � π π π π 1 � = = = = 3 �� Low frequency PSD is increased by 2 � � � �� , τ τ τ τ 2 � � � � 13 Sampled Thermal Noise � 1/f 3dB is the settling time of the system, while 1/2f S is the settling period for a two�phase clock 1/ 2 � � − − − − < < < < − − − − + + + + ( � 1) � τ τ τ τ 2 π π π π � > > > > + + + + 3 �� ( � 1)ln2 � � � + + + + ( 1)ln2 PSD is increased by at least If N = 10 bits, PSD is increased by 7.6, or 8.8dB � This is an inherent disadvantage of sampled� data compared to continuous�time systems But noise is reduced by oversampling ratio after digital filtering 14
Noise in a SC Integrator � Using the parasitic�insensitive SC integrator � Two phases to consider 1) Sampling Phase Includes noise from both φ φ 1 switches φ φ 2) Integrating Phase Includes noise from both φ φ 2 switches and OTA φ φ 15 Noise in a SC Integrator � Phase 1: Sampling = = = = � ( ) � 8 ��� Noise PSD from two switches: ��� �� τ τ τ τ = = = = 2 � � Time constant of R�C filter: �� 1 PSD of noise voltage across C 1 8 ��� = = = = �� � ( ) � � 1 + + + + π τ π τ π τ π τ 2 1 (2 � ) 16
Noise in a SC Integrator � Phase 1: Sampling Integrated across entire spectrum, total noise power in C 1 is 8 ��� �� 2 = = = = = = = = � �� � 1, �� 1 τ τ τ τ 4 � 1 Independent of R ON (PSD is proportional to R ON , bandwidth is inversely proportional to R ON ) After sampling, charge is trapped in C 1 17 Noise in a SC Integrator � Phase 2: Integrating � Two noise sources: switches and OTA = = = = Noise PSD from two switches: � ( ) � 8 ��� ��� �� 16 �� = = = = � ( ) � � Noise PSD from OTA: �� �� , � 3 � � 1 2 + + + + 2 Noise power across C 1 charges to 2 � � ��� � �� , 18
Noise in a SC Integrator � What is the time�constant? + + + + 1/ �� � = = = = Analysis shows that 2 � � �� + + + + 1 � � � 1 � 1 ≈ ≈ ≈ ≈ For large R L , assume that � �� � � 1 τ = τ τ τ = = = + + + + (2 � 1/ � ) � Resulting time constant �� � 1 1 19 Noise in a SC Integrator � Total noise power with both switches and OTA on integrating phase � ( ) � � ( ) � = = = = 2 ��� 2 = = = = �� �� , � � � 1, �� 2 τ τ τ τ � �� 1, τ τ 4 τ τ 4 8 ��� 16 �� � = = = = �� = = = = � + + + + + + + + 4(2 � 1/ � ) � 3 � 4(2 � 1/ � ) � �� � 1 1 � 1 �� � 1 1 �� � 4 �� � = = = = = = = = � + + + + � (1 � ) + + + + 3 � (1 � ) 1 1 = = = = Introduced extra parameter � 2 � � �� � 1 20
Noise in a SC Integrator � Total noise power on C1 from both phases 2 = = = = 2 + + + + 2 + + + + 2 � � � � � 1 � �� 1, � 1, �� 1 � 1, �� 2 4 �� � �� � �� = = = = + + + + + + + + � + + + + + + + + 3 � (1 � ) � (1 � ) � 1 1 1 + + + + + + + + �� 4 � / 3 1 2 � = = = = � + + + + � 1 � 1 � → ∞ → ∞ → ∞ → ∞ Lowest possible noise achieved if 2 �� 2 = = = = � In this case, � 1 � 1 What was assumed to be the total noise was actually the least possible noise! 21 Noise Contributions � Percentage noise contribution from switches and OTA (assume n f =1.5) ��� ������ � ! �� ������������������ �� �� �� � � � � � � �� ���� �� � �� 22
Noise Contributions � When g m1 >> 1/R ON (x >> 1)# Switch dominates both bandwidth and noise Total noise power is minimized � When g m1 << 1/R ON (x << 1)# OTA dominates both bandwidth and noise Power�efficient solution Minimize g m1 (and power) for a given settling time and noise �� 4 = = = = + + + + + + + + � � 1 2 � � 1 � 3 τ τ τ τ 2 � � 1 Minimized for x=0 23 Maximum Noise � How much larger can the noise get? Depends on n f # (table excludes cascode noise) Maximum Architecture Relative V EFF ’s n f +dB Noise (x=0) Telescopic/ V EFF,1 =V EFF,n /2 1.5 3 . kT/C 1 1.76 Diff.Pair Telescopic/ V EFF,1 =V EFF,n 2 3.67 . kT/C 1 2.63 Diff.Pair Folded V EFF,1 =V EFF,n /2 2.5 4.33 . kT/C 1 3.36 Cascode Folded V EFF,1 =V EFF,n 4 6.33 . kT/C 1 5.01 Cascode 24
Recommend
More recommend
