https://ntrs.nasa.gov/search.jsp?R=20170005805 2017-12-10T00:44:12+00:00Z NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing Melanie Berg, AS&D Inc. in support of the NEPP Program and NASA/GSFC Melanie.D.Berg@NASA.gov Kenneth LaBel: NASA/GSFC Michael Campola: NASA/GSFC Jonathan Pellish: NASA/GSFC To be presented by Melanie Berg at the NASA Electronic Parts and Packaging (NEPP) Program Electronics Technology Workshop (ETW), NASA To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June26 – 29, 2017 Goddard Space Flight Center in Greenbelt, MD, June 13-16, 2016.
Acronyms Acronym Definition Acronym Definition 1MB 1 Megabit NRL Naval Research Laboratory 3D Three Dimensional Acronym Definition 3DIC Three Dimensional Integrated Circuits NRO National Reconnaissance Office GSN Goal Structured Notation ACE Absolute Contacting Encoder OCM On-chip RAM GTH/GTY Transceiver Type AHB Advanced high performance bus PC Personal Computer GTMR Global TMR PCB Printed Circuit Board ADC Analog to Digital Converter HALT Highly Accelerated Life Test AEC Automotive Electronics Council PCIe Peripheral Component Interconnect Express HAST Highly Accelerated Stress Test AES Advanced Encryption Standard PCIe Gen2 Peripheral Component Interconnect Express Generation 2 HBM High Bandwidth Memory AF Air Force HDIO High Density Digital Input/Output Pconfiguration SEU cross-section of configuration AFRL Air Force Research Laboratory Pfunctional_logic SEU cross-section of functional logic HDR High-Dynamic-Range AMD Advanced Micro Devices Incorporated PHY Physical layer HiREV High Reliability Virtual Electronics Center AMS Agile Mixed Signal PLL Phase Locked Loop HMC Hybrid Memory Cube ARM Acorn Reduced Instruction Set Computer Machine PMA Physical Medium Attachment HOST Hardware Oriented Security and Trust AXI Advanced extensible interface POR Power on reset HP Labs Hewlett-Packard Laboratories BAE British Aerospace Proc. Processing HPIO High Performance Input/Output BGA Ball Grid Array PS-GTR High Speed Bus Interface HPS High Pressure Sodium BOK Body of Knowledge PSEFI SEU cross-section from single event functional interrupts HSTL High speed transceiver logic BTMR Block triple modular redundancy I/F interface Psystem System SEU cross-section BYU Brigham Young University I/O QDR quad data rate input/output CAN Controller Area Network QFN Quad Flat Pack No Lead I2C Inter-Integrated Circuit CBRAM Conductive Bridging Random Access Memory i2MOS Microsemi second generation of Rad-Hard MOSFET QML Qualified manufactures list CCI Correct Coding Initiative IC Integrated Circuit QSPI Serial Quad Input/Output CGA Column Grid Array I-Cache independent cache RADECS IEEE Radiation and its Effects on Components and Systems CMOS Complementary Metal Oxide Semiconductor RC Resistor capacitor JFAC Joint Federated Assurance Center Xilinx ceramic flip-chip (CF and CN) packages are ceramic column CN JPEG Joint Photographic Experts Group R&M Reliability and Maintainability grid array (CCGA) packages JPL Jet propulsion laboratory RAM Random Access Memory COTS Commercial Off The Shelf Joint Test Action Group (FPGAs use JTAG to provide ReRAM Resistive Random Access Memory JTAG CRC Cyclic Redundancy Check access to their programming debug/emulation functions) RGB Red, Green, and Blue CRÈME Cosmic Ray Effects on Micro Electronics KB Kilobyte RH Radiation Hardened CRÈME MC Cosmic Ray Effects on Micro Electronics Monte Carlo L2 Cache independent caches organized as a hierarchy (L1, L2, etc.) RT Radiation Tolerant CSE Crypto Security Engin SATA Serial Advanced Technology Attachment CU Control Unit LCDT NEPP low cost digital tester SCU Secondary Control Unit D-Cache defered cache LEO Low Earth Orbit SD Secure Digital DCU Distributed Control Unit LET Linear energy transfer SD/eMMC Secure Digital embedded MultiMediaCard DDR Double Data Rate (DDR3 = Generation 3; DDR4 = Generation 4) L-mem Long-Memory SD-HC Secure Digital High Capacity DFF Flip-flop LANL Los Alamos National Laboratory SDM Spatial-Division-Multiplexing DMA Direct Memory Access LP Low Power SEE Single Event Effect DSP Digital Signal Processing LUT Look-up table SEFI Single Event Functional Interrupt dSPI Dynamic Signal Processing Instrument Low-voltage Complementary Metal Oxide Semiconductor LVCMOS SEL Single event latchup DTMR Distributed triple modular redundancy LVDS Low-Voltage Differential Signaling SERDES Serializer/deserializer Dual Ch. Dual Channel LVTTL Low – voltage transistor-transistor logic SET Single event transient DUT Device under test LTMR Local triple modular redundancy ECC Error-Correcting Code SEU Single event upset LW HPS Lightwatt High Pressure Sodium Si Silicon EDAC Error detection and correction M/L BIST Memory/Logic Built-In Self-Test SK Hynix SK Hynix Semiconductor Company EEE Electrical, Electronic, and Electromechanical Mil-STD Military standard SMDs Selected Item Descriptions EMAC Equipment Monitor And Control MAPLD Military Aerospace Programmable Logic Device SMMU System Memory Management Unit EMIB Multi-die Interconnect Bridge MBMA Model-Based Missions Assurance SNL Sandia National Laboratories EPCS Extended physical coding layer MFTF Mean fluence to failure ESA European Space Agency SOA Safe Operating Area μPROM Micro programmable read-only memory eTimers Event Timers SOC Systems on a Chip μSRAM Micro SRAM ETW Electronics Technology Workshop SPI Serial Peripheral Interface Mil/Aero Military/Aerospace FCCU Fluidized Catalytic Cracking Unit SSTL Sub series terminated logic MIPI Mobile Industry Processor Interface FeRAM Ferroelectric Random Access Memory TBD To Be Determined MMC MultiMediaCard FinFET Fin Field Effect Transistor Temp Temperature MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor FIR Finite impulse response filter THD+N Total Harmonic Distortion Plus Noise MP Microprocessor FPGA Field Programmable Gate Array TMR Triple Modular Redundancy MP Multiport FPU Floating Point Unit T-Sensor Temperature-Sensor MPFE Multiport Front-End FY Fiscal Year TSMC Taiwan Semiconductor Manufacturing Company MPSoC Multiprocessor System on a chip Gb Gigabit UART Universal Asynchronous Receiver/Transmitter MPU Microprocessor Unit Gbps Gigabit per second Ultra Random Access Memory Msg message UltraRAM GCR Galactic Cosmic Ray USB Universal Serial Bus MTTF Mean time to failure geostationary equatorial orbit GEO NAND Negated AND or NOT AND VNAND Vertical NAND GIC Global Industry Classification WDT Watchdog Timer NASA National Aeronautics and Space Administration Government Microcircuit Applications and Critical Technology GOMACTech NASA STMD NASA's Space Technology Mission Directorate Conference WSR Windowed shift register Navy Crane Naval Surface Warfare Center, Crane, Indiana XAUI Extended 10 Gigabit Media Independent Interface GPIO General purpose input/output XGXS 10 Gigabit Ethernet Extended Sublayer GPU Graphics Processing Unit NEPP NASA Electronic Parts and Packaging NGSP Next Generation Space Processor XGMII 10 Gigabit Media Independent Interface) GRC NASA Glenn Research Center NOR Not OR logic gate XWSG Xilinx Security Working Group GSFC Goddard Space Flight Center 2 To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June26 – 29, 2017
Outline • FPGA test guidelines • Microsemi RTG4 heavy-ion results. • Xilinx Kintex-UltraScale heavy-ion results. • Xilinx UltraScale+ single event effect (SEE) test plans. • Development of a new methodology for characterizing SEU system response. • NEPP involvement with FPGA security and trust. 3 To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June26 – 29, 2017
NEPP – Processors, Systems on a Chip (SOC), and Field Programmable Gate Arrays (FPGAs) State of the Art “Space” FPGAs COTS • Microsemi RTG4 Processors • Xilinx MPSOC+ • Sub 32nm CMOS, • ESA Brave (future) FinFETs, etc • “Trusted” FPGA • Samsung, Intel, (future) AMD Graphics COTS FPGAs Processor • Xilinx Kintex+ Units (GPUs) • Mitigation evaluation • Intel, AMD, Nvidia • TBD: Microsemi • Enabling data PolarFire processing Partnering • Processors: Navy Radiation Best Crane, BAE/NRO- Hardened • FPGAs: AF, Practices Processor Aerospace, SNL, LANL, BYU,… Evaluation and • Microsemi, Xilinx, • BAE Synopsis Guidelines • Vorago • Cubic Aerospace (microcontrollers) Potential future task areas: artificial intelligence (AI) hardware, Intel Stratix 10 To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June26 – 29, 2017
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