Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - PowerPoint PPT Presentation

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

2 2 Date: March 02, 2011 Date: March 02, 2011 Data Converters Data Converters Contents Contents  Performance Specifications of Data Converters  ADC and DAC Architectures  Flash ADC IIT-Bombay Lecture 12 M. Shojaei Baghini

3 3 Ideal Characteristic of ADC Center point 1 LSB IIT-Bombay Lecture 12 M. Shojaei Baghini

4 4 Quantization Error in Ideal ADC FS/2 N For a sine wave signal x(t) and approximate uniform distribution of q e Example: N = 6 bits ⇒ SNR=37.9dB N = 10 bits ⇒ SNR=62.0dB IIT-Bombay Lecture 12 M. Shojaei Baghini

5 5 Incorporating Nonlinearities of ADC - THD (Total Harmonic Distortion) - SINAD (or SNDR) (Signal to Noise and Distortion Ratio) SINAD: Ratio of rms value of the input signal to the rms sum of all other spectral components. IIT-Bombay Lecture 12 M. Shojaei Baghini

6 6 Frequency Domain - ADC Nonlinearity FFT f s =200MS/s f 0 =45.0195MHz Harmonics? Nicolas Gray, National Semiconductor, 2006 IIT-Bombay Lecture 12 M. Shojaei Baghini

7 7 Dynamic Range In general dynamic range is the ratio of largest absolute value of the signal to the smallest absolute value of the signal. In an ideal ADC, dynamic range = 20.log2 N ≈ 6NdB. Some times dynamic range is defined as SNR itself. Spurious-Free Dynamic Range (SFDR): Ratio of the input signal to the peak harmonic (or spurious)component. IIT-Bombay Lecture 12 M. Shojaei Baghini

8 8 SFDR - Example Noise floor Nicolas Gray, National Semiconductor, 2006 IIT-Bombay Lecture 12 M. Shojaei Baghini

9 9 Static and Time Domain Specifications Offset and Gain Error Slope < 2 N /FS (Gain error in codes/per signal unit) Center point 1 LSB Offset error Offset error IIT-Bombay Lecture 12 M. Shojaei Baghini

10 10 Static and Time Domain Specifications – DNL (Differential Nonlinearity) of ADC Understanding Data Converters, TI, 1995 Sometimes only maximum |DNL| is given in data sheets. IIT-Bombay Lecture 12 M. Shojaei Baghini

11 11 Static and Time Domain Specifications – DNL (Differential Nonlinearity) of DAC Understanding Data Converters, TI, 1995 Sometimes only maximum |DNL| is given in data sheets. IIT-Bombay Lecture 12 M. Shojaei Baghini

12 12 Static and Time Domain Specifications – INL (Integrated Nonlinearity) Understanding Data Converters, TI, 1995 INL is measured after the offset is corrected to zero. IIT-Bombay Lecture 12 M. Shojaei Baghini

13 13 Main Time Domain Specifications - Conversion Time - Sampling Rate - Sampling-Time Uncertainty IIT-Bombay Lecture 12 M. Shojaei Baghini

14 14 Flash ADC Architecture and an example considering variations in the resistive network and comparator offset voltages is explained in the lecture. IIT-Bombay Lecture 12 M. Shojaei Baghini

15 15 End of lecture 12 IIT-Bombay Lecture 12 M. Shojaei Baghini

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - PowerPoint PPT Presentation

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: March 02, 2011 Date: March 02, 2011 Data

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester:

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester:

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester:

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