Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - PowerPoint PPT Presentation

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 32: March 26, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

2 2 Module 42 Basic Concepts of 1-bit Pipeline ADC Reference: Section 17.4 Analog Integrated Circuit Design T. C. Caruson, D. A. Johns and K. W. Martin, 2012 IIT-Bombay Lecture 32 M. Shojaei Baghini

3 3 Nyquist ADCs (Clock-based Classification) Source: B. Murmann 2013 IIT-Bombay Lecture 32 M. Shojaei Baghini

4 4 Performance of Data Converters, 2017 Speed, SNDR IIT-Bombay Lecture 32 M. Shojaei Baghini

5 5 Signal Flow in Pipelined ADC Ken Martin’s book, 2012 edition IIT-Bombay Lecture 32 M. Shojaei Baghini

6 6 1-bit Pipelined Converter Stage Notice: V ref = V FS - The expression is simplified based on b i =0 or b i =1. Notice: b i corresponds to the pipelined stage number. IIT-Bombay Lecture 32 M. Shojaei Baghini

7 7 1-bit Pipelined Converter Stage MDAC: Multiplying DAC Notice: V ref = V FS - Quantized equivalent of the ADC output (given to an ideal DAC) Notice: b i corresponds to the Ken Martin’s book, pipelined stage number. 2012 edition IIT-Bombay Lecture 32 M. Shojaei Baghini

8 8 Block Diagram of 1-bit Pipelined ADC IIT-Bombay Lecture 32 M. Shojaei Baghini

9 9 End of Lecture 32 IIT-Bombay Lecture 32 M. Shojaei Baghini