Instruction Set Architecture 9/20/16 Overview How to directly - PowerPoint PPT Presentation

Instruction Set Architecture 9/20/16

Overview • How to directly interact with hardware • Instruction set architecture (ISA) • Interface between programmer and CPU • Established instruction format (assembly lang) • Assembly programming (IA-32)

Abstraction User / Programmer Wants low complexity Applications Specific functionality Software library Reusable functionality Operating system Manage resources Complex devices Compute & I/O

Abstraction Applications Specific functionality This week: Machine Interface Operating system Manage resources Complex devices Last week: Circuits, Hardware Implementation Compute & I/O

Compilation Steps (.c to a.out) C program ( p1.c ) text Usually compile to a.out in a single step: gcc –m32 p1.c -m32 tells gcc to compile for 32-bit Intel machines Compiler ( gcc –m32 ) Reality is more complex: there are intermediate steps! executable Executable code ( a.out ) binary

Compilation Steps (.c to a.out) C program ( p1.c ) text You can see the results of intermediate compilation steps using different gcc flags CS75 Compiler ( gcc –m32 -S ) Assembly program ( p1.s ) text executable Executable code ( a.out ) binary

Assembly Code Human-readable form of CPU instructions • Almost a 1-to-1 mapping to Machine Code • Hides some details: • Registers have names rather than numbers • Instructions have names rather than variable-size codes We’re going to use IA32 (x86) assembly CS lab machines are 64 bit version of this ISA, but they can • also run the 32-bit version (IA32) Can compile C to IA32 assembly on our system: • # open code.s in vim to view gcc –m32 -S code.c

Compilation Steps (.c to a.out) C program ( p1.c ) text You can see the results of intermediate compilation steps using different gcc flags Compiler ( gcc –m32 -S ) Assembly program ( p1.s ) text Assembler ( gcc -c ( or as )) Other object files Object code ( p1.o ) binary (p2.o, p3.o, …) Linker ( gcc (or ld) ) Library obj. code ( libc.a ) executable Executable code ( a.out ) binary

Object / Executable / Machine Code int main() { Assembly Machine Code (Hexadecimal) push %ebp 55 int a = 10; mov %esp, %ebp 89 E5 int b = 20; sub $16, %esp 83 EC 10 movl $10, -8(%ebp) C7 45 F8 0A 00 00 00 movl $20, -4(%ebp) C7 45 FC 14 00 00 00 a = a + b; movl -4(%ebp), $eax 8B 45 FC addl $eax, -8(%ebp) 01 45 F8 return a; movl -8(%ebp), %eax B8 45 F8 } leave C9

Compilation Steps (.c to a.out) C program ( p1.c ) text High-level language Compiler ( gcc –m32 -S ) Interface for speaking to CPU Assembly program ( p1.s ) text Assembler ( gcc -c ( or as )) CPU-specific format (011010…) Other object files Object code ( p1.o ) binary (p2.o, p3.o, …) Linker ( gcc (or ld) ) Library obj. code ( libc.a ) executable Executable code ( a.out ) binary

Instruction Set Architecture (ISA) • ISA (or simply architecture): Interface between lowest software level and the hardware. • Defines specification of the language for controlling CPU state: • Provides a set of instructions • Makes CPU registers available • Allows access to main memory • Exports control flow (change what executes next)

Instruction Set Architecture (ISA) • The agreed-upon interface between all software that runs on the machine and the hardware that executes it. Application / Program Operating System Compiler Instruction Set Architecture CPU / Processor I/O system Digital Circuits Logic Gates

ISA Examples • Intel IA-32 (80x86) • Intel IA-64 (Itanium) • ARM • VAX • MIPS • SPARC • PowerPC • Alpha • IBM Cell • IBM 360 • Motorola 68k How many of these have you used?

High-level language ISA Characteristics ISA Hardware Implementation • Above ISA: High-level language (C, Python, …) • Hides ISA from users • Allows a program to run on any machine (after translation by human and/or compiler) • Below ISA: Hardware implementing ISA can change (faster, smaller, …) • ISA is like a CPU “family”

Instruction Translation sum.c (High-level C) int sum(int x, int y) sum.s from sum.c: { gcc –m32 –S sum.c int res; res = x+y; return res; } sum.s (Assembly) sum: Instructions to set up the stack pushl %ebp frame and get argument values movl %esp,%ebp subl $24, %esp movl 12(%ebp),%eax An add instruction to compute sum addl 8(%ebp),%eax movl %eax, -12(%ebp) leave Instructions to return from function ret

ISA Design Questions sum.c (High-level C) int sum(int x, int y) sum.s from sum.c: { gcc –m32 –S sum.c int res; res = x+y; return res; } sum.s (Assembly) sum: What should these instructions do? pushl %ebp movl %esp,%ebp What is/isn’t allowed by hardware? subl $24, %esp movl 12(%ebp),%eax How complex should they be? addl 8(%ebp),%eax movl %eax, -12(%ebp) leave Example: supporting multiplication. ret

C statement: A = A*B Simple instructions: Powerful instructions: LOAD A, eax MULT B, A LOAD B, ebx PROD eax, ebx STORE ebx, A Translation: Load the values ‘A’ and ‘B’ from memory into registers, compute the product, store the result in memory where ‘A’ was.

Which would you use if you were designing an ISA for your CPU? (Why?) Simple instructions: Powerful instructions: LOAD A, eax MULT B, A LOAD B, ebx PROD eax, ebx STORE ebx, A A. Simple B. Powerful C. Something else

RISC versus CISC (Historically) • Complex Instruction Set Computing (CISC) • Large, rich instruction set • More complicated instructions built into hardware • Multiple clock cycles per instruction • Easier for humans to reason about • Reduced Instruction Set Computing (RISC) • Small, highly optimized set of instructions • Memory accesses are specific instructions • One instruction per clock cycle • Compiler: more work, more potential optimization

So . . . Which System “Won”? • Most ISAs (after mid/late 1980’s) are RISC • The ubiquitous Intel x86 is CISC • Tablets and smartphones (ARM) taking over? • x86 breaks down CISC assembly into multiple, RISC- like, machine language instructions • Distinction between RISC and CISC is less clear • Some RISC instruction sets have more instructions than some CISC sets

Intel x86 Family (IA-32) Intel i386 (1985) Intel Core i7 4770k (2013) • 12 MHz - 40 MHz • 3,500 MHz • ~300,000 transistors • ~1,400,000,000 transistors • Component size: 1.5 µm • Component size: 22 nm Everything in this family uses the same ISA (Same instructions)!

Assembly Programmer’s View of State CPU 32-bit Registers Memory name value BUS %eax address value %ecx 0x00000000 Addresses %edx 0x00000001 %ebx Data … %esi Program: %edi Instructions %esp data %ebp instrs % eip next instr stack addr (PC) % EFLAGS cond. codes 0xffffffff Registers: Memory: PC : Program counter ( %eip ) • Byte addressable array Condition codes ( %EFLAGS ) • Program code and data General Purpose ( %eax - %ebp ) • Execution stack

Processor State in Registers %eax • Information about %ecx currently executing %edx program General purpose registers %ebx • Temporary data ( %eax - %edi ) %esi • Location of runtime stack %edi ( %ebp , %esp ) %esp Current stack top • Location of current code %ebp Current stack frame control point ( %eip , … ) • Status of recent tests %eip Instruction pointer (PC) %EFLAGS ( CF , ZF , SF , OF ) Condition codes CF ZF SF OF

General purpose Registers • Remaining Six are for instruction operands • Can store 4 byte data or address value (ex. 3 + 5) The low-order 2 bytes and two low-order 1 Register Register name value bytes of some of these can be named. %eax 3 %ax is the low-order 16 bits of %eax %al is the low-order 8 bits of %eax %ecx 5 May see their use in ops involving shorts or chars %edx 8 31 16 15 8 7 0 %eax %ax %ah %al %ebx %ecx %cx %ch %cl %esi %edx %dx %dh %dl %ebx %bx %bh %bl %edi %esi %si %esp %edi %di %ebp %esp %sp %eip %ebp %bp %EFLAGS

Types of IA32 Instructions • Data movement • Move values between registers and memory • example: movl • Arithmetic • Uses ALU to compute a value • example: addl • Control • Change PC based on ALU condition code state • example: jmp

Data Movement Move values between memory and registers or between two registers. (Memory) Program Counter (PC): Memory address of next instr 0: 1: Instruction Register (IR): Instruction contents (bits) 2: 3: 4: … Data in N-1: 32-bit Register #0 WE MUX Data in 32-bit Register #1 A WE L Data in 32-bit Register #2 U WE MUX Data in … 32-bit Register #3 WE Register File

Arithmetic Use ALU to compute a value, store result in register / memory. (Memory) Program Counter (PC): Memory address of next instr 0: 1: Instruction Register (IR): Instruction contents (bits) 2: 3: 4: … Data in N-1: 32-bit Register #0 WE MUX Data in 32-bit Register #1 A WE L Data in 32-bit Register #2 U WE MUX Data in … 32-bit Register #3 WE Register File

Control Change PC based on ALU condition code state. (Memory) Program Counter (PC): Memory address of next instr 0: 1: Instruction Register (IR): Instruction contents (bits) 2: 3: 4: … Data in N-1: 32-bit Register #0 WE MUX Data in 32-bit Register #1 A WE L Data in 32-bit Register #2 U WE MUX Data in … 32-bit Register #3 WE Register File